NetBSD Problem Report #45080
From tsutsui@ceres.dti.ne.jp Fri Jun 17 16:03:39 2011
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Message-Id: <201106171603.p5HG3VTi029175@mirage.localdomain>
Date: Sat, 18 Jun 2011 01:03:31 +0900 (JST)
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
Reply-To: tsutsui@ceres.dti.ne.jp
To: gnats-bugs@gnats.NetBSD.org
Cc: tsutsui@ceres.dti.ne.jp
Subject: emips GENERIC kernel doesn't boot
X-Send-Pr-Version: 3.95
>Number: 45080
>Category: port-emips
>Synopsis: emips GENERIC kernel doesn't boot
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: tsutsui
>State: closed
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Fri Jun 17 16:05:00 +0000 2011
>Closed-Date: Sat Dec 14 13:33:30 +0000 2019
>Last-Modified: Sat Dec 14 13:33:30 +0000 2019
>Originator: Izumi Tsutsui
>Release: NetBSD 5.99.52
>Organization:
>Environment:
System: NetBSD/emips 5.99.52 around 20110612 on Microsoft Giano on Windows XP
Architecture: mipseb
Machine: emips
>Description:
NetBSD/emips GENERIC kernel hangs right after interrupts are enabled.
It spins in cpu_intr() because splintr() returns ipending==MIPS_INT_MASK_5
while no interrupts are asserted in TheAic->IrqStatus in emips_aic_intr().
5.99.44 GENERIC kernel around 20110130 worked fine.
>How-To-Repeat:
Boot -current NetBSD/emips GENERIC kernel on Microsoft Giano.
>Fix:
Unknown.
>Release-Note:
>Audit-Trail:
From: coypu@sdf.org
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-emips/45080: emips GENERIC kernel doesn't boot
Date: Sat, 30 Nov 2019 20:46:11 +0000
from phone: the prototype of emips cpu_intr is wrong (it has two fields
confused).
From: coypu@sdf.org
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-emips/45080: emips GENERIC kernel doesn't boot
Date: Sun, 1 Dec 2019 20:37:46 +0000
mips/include/cpu.h#219
cpu_intr(ppl, pc, status);
emips/interrupt.c#98
cpu_intr(ppl, status, pc);
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
To: gnats-bugs@netbsd.org
Cc: coypu@sdf.org, tsutsui@ceres.dti.ne.jp
Subject: Re: port-emips/45080: emips GENERIC kernel doesn't boot
Date: Wed, 4 Dec 2019 00:35:13 +0900
So bad.
I'll re-setup giano.
https://wiki.netbsd.org/users/ryoon/how_to_install_netbsd_emips_current_to_microsoft_giano/
https://www.microsoft.com/en-us/download/details.aspx?id=52407
---
Izumi Tsutsui
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
To: gnats-bugs@netbsd.org
Cc: coypu@sdf.org, tsutsui@ceres.dti.ne.jp
Subject: Re: port-emips/45080: emips GENERIC kernel doesn't boot
Date: Fri, 6 Dec 2019 03:43:57 +0900
> I'll re-setup giano.
> https://wiki.netbsd.org/users/ryoon/how_to_install_netbsd_emips_current_to_microsoft_giano/
> https://www.microsoft.com/en-us/download/details.aspx?id=52407
As I wrote in the PR, I guess the essential problem is
STATUS and CAUSE register implementation of the eMIPS:
>> NetBSD/emips GENERIC kernel hangs right after interrupts are enabled.
>> It spins in cpu_intr() because splintr() returns ipending==MIPS_INT_MASK_5
>> while no interrupts are asserted in TheAic->IrqStatus in emips_aic_intr().
With the following ugly patch (I tried back in 2011) and
the newly identified cpu_intr() args fix, NetBSD/emips 9.0_RC1
GENERIC kernel boots upto multiuser. Oh well.
---
Index: emips/interrupt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/emips/emips/interrupt.c,v
retrieving revision 1.6
diff -u -p -d -r1.6 interrupt.c
--- emips/interrupt.c 11 Jul 2016 16:18:56 -0000 1.6
+++ emips/interrupt.c 5 Dec 2019 17:38:29 -0000
@@ -95,7 +95,7 @@ intr_init(void)
* emips uses one line for all I/O interrupts (0x8000).
*/
void
-cpu_intr(int ppl, uint32_t status, vaddr_t pc)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
uint32_t ipending;
int ipl;
@@ -103,6 +103,10 @@ cpu_intr(int ppl, uint32_t status, vaddr
curcpu()->ci_data.cpu_nintr++;
while (ppl < (ipl = splintr(&ipending))) {
+#if 1 /* BUGBUG incomplete interrupt controller masks */
+ if (TheAic->IrqStatus == 0)
+ break;
+#endif
splx(ipl);
/* device interrupts */
if (ipending & MIPS_INT_MASK_5) {
---
---
Hit any char to boot..
NetBSD/emips 9.0_RC1 Netboot Bootstrap, Revision 1.0 (Wed Nov 27 16:14:52 UTC 2019)
Default: 0/ace(0,0)/netbsd
boot:
Loading: 0/ace(0,0)/netbsd
3674512+107184 [212608+202659]=0x4010ac
Starting at 0x80020000
[ 1.0000000] memory segment 0 start 00000000 size 10000000
[ 1.0000000] memory segment 1 start 10000000 size 00100000
[ 1.0000000] Too much memory in cluster 0, trimming memory to range 00000000..08000000
[ 1.0000000] Too much memory, ignoring memory range 10000000..10100000
[ 1.0000000] Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
[ 1.0000000] 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017,
[ 1.0000000] 2018, 2019 The NetBSD Foundation, Inc. All rights reserved.
[ 1.0000000] Copyright (c) 1982, 1986, 1989, 1991, 1993
[ 1.0000000] The Regents of the University of California. All rights reserved.
[ 1.0000000] NetBSD 9.0_RC1 (GENERIC) #7: Thu Dec 5 02:28:51 JST 2019
[ 1.0000000] tsutsui@mirage:/s/netbsd-9/src/sys/arch/emips/compile/GENERIC
[ 1.0000000] Xilinx ML50x (eMIPS)
[ 1.0000000] total memory = 128 MB
[ 1.0000000] avail memory = 121 MB
[ 1.0000000] mainbus0 (root)
[ 1.0000000] cpu0 at mainbus0: Toshiba or Microsoft eMIPS CPU (0x70401) Rev. 1 with software emulated floating point
[ 1.0000000] cpu0: 64 TLB entries
[ 1.0000000] ebus0 at mainbus0
[ 1.0000000] eclock0 at ebus0 addr 0xfff80000: eMIPS clock
[ 1.0000050] dz0 at ebus0 addr 0xfff90000: neilsart 1 line
[ 1.0000050] ace0 at ebus0 addr 0xfff50000 : System ACE
[ 1.0000050] ace1 at ebus0 addr 0xfff50100 : System ACE
[ 1.0000050] enic0 at ebus0 addr 0xfff10000: eNIC [1 0], address 02:00:00:02:00:00
[ 1.0000050] icap0 at ebus0 addr 0xffed0000: Internal Configuration Access Port
[ 1.0000050] epio0 at ebus0 addr 0xfff60000: GPIO controller
[ 1.0000050] gpio0 at epio0: 32 pins
[ 1.0000050] eflash0 at ebus0 addr 0xfffb0000 base f0000000: 8MB flash memory (2 x StrataFlash 28F320)
[ 1.0000050] lcd at ebus0 addr 0xfff40000 not configured
[ 1.0000050] evga at ebus0 addr 0xfff20000 not configured
[ 1.0000050] ps2 at ebus0 addr 0xfff30000 not configured
[ 1.0000050] ac97 at ebus0 addr 0xffef0000 not configured
[ 1.0000050] eflash0: 8192 KB, 1 cyl, 1 head, 16384 sec, 512 bytes/sect x 16384 sectors
[ 1.0000050] ace0: drive supports 255-sector PIO xfers
[ 1.0000050] ace0: card is <SanDisk SDCFB-32>
[ 1.0000050] ace0: 4096 MB, 256 cyl, 1 head, 32768 sec, 512 bytes/sect x 8388608 sectors
[ 1.0000050] ace1: drive supports 255-sector PIO xfers
[ 1.0000050] ace1: card is <SanDisk SDCFB-32>
[ 1.0000050] ace1: 259 MB, 16 cyl, 1 head, 32768 sec, 512 bytes/sect x 531076 sectors
[ 2.0226181] boot device: ace0 part0
[ 2.0226181] root on ace0a dumps on ace0b
[ 2.0226181] root file system type: ffs
[ 2.0871086] kern.module.path=/stand/emips/9.0/modules
[ 3.1746543] dzparam: c_ispeed 9600 ignored, keeping 38400
Fri Dec 6 03:34:34 JST 2019
Starting root file system check:
/dev/race0a: file system is clean; not checking
eval: handle_fsck_error: not found
swapctl: adding /dev/ace0b as swap device at priority 0
Starting file system checks:
eval: handle_fsck_error: not found
random_seed: /var/db/entropy-file: Not present
Setting tty flags.
Setting sysctl variables:
ddb.onpanic: 1 -> 0
Starting network.
Hostname: emips
IPv6 mode: host
Configuring network interfaces:.
Adding interface aliases:.
eval: checkyesnox: not found
Waiting for DAD to complete for statically configured addresses...
Building databases: dev.
Starting syslogd.
Could not open /dev/crypto: Device not configured
Mounting all file systems...
Clearing temporary files.
Updating fontconfig cache: done.
Checking quotas: done.
Setting securelevel: kern.securelevel: 0 -> 1
Starting virecover.
Checking for core dump...
savecore: no core dump
Starting local daemons:.
Updating motd.
postfix: Postfix is running with backwards-compatible default settings
postfix: See http://www.postfix.org/COMPATIBILITY_README.html for details
postfix: To disable backwards compatibility use "postconf compatibility_level=2" and "postfix reload"
postfix/postfix-script: starting the Postfix mail system
Starting inetd.
Starting cron.
Fri Dec 6 03:37:03 JST 2019
NetBSD/emips (emips) (console)
login: root
Dec 6 03:37:13 emips login: ROOT LOGIN (root) on tty console
Last login: Fri Dec 6 03:31:52 2019 on console
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017,
2018, 2019 The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 9.0_RC1 (GENERIC) #7: Thu Dec 5 02:28:51 JST 2019
Welcome to NetBSD!
You have mail.
Terminal type is vt100.
We recommend creating a non-root account and using su(1) for root access.
emips#
---
(BTW, postinstall(8) fix doesn't update /etc/rc.subr ?)
---
Izumi Tsutsui
Responsible-Changed-From-To: port-emips-maintainer->tsutsui
Responsible-Changed-By: tsutsui@NetBSD.org
Responsible-Changed-When: Sat, 07 Dec 2019 17:24:53 +0000
Responsible-Changed-Why:
I have a workaround patch.
State-Changed-From-To: open->analyzed
State-Changed-By: tsutsui@NetBSD.org
State-Changed-When: Sat, 07 Dec 2019 17:24:53 +0000
State-Changed-Why:
I'll commit the workaround fix if there is no further comment.
From: "Izumi Tsutsui" <tsutsui@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/45080 CVS commit: src/sys/arch/emips/emips
Date: Mon, 9 Dec 2019 16:19:12 +0000
Module Name: src
Committed By: tsutsui
Date: Mon Dec 9 16:19:11 UTC 2019
Modified Files:
src/sys/arch/emips/emips: interrupt.c
Log Message:
Fix incorrect argument order of cpu_intr(), slipped in rev 1.2.
Pointed out by maya@ in PR/45080.
Should be pulled up to netbsd-9.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/emips/emips/interrupt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
To: gnats-bugs@netbsd.org
Cc: tsutsui@ceres.dti.ne.jp
Subject: Re: port-emips/45080 (emips GENERIC kernel doesn't boot)
Date: Wed, 11 Dec 2019 00:41:01 +0900
Now I've checked the Giano simulator implementation, then
it turns out eMIPS CPU core simulated by Giano updates interrupt
register bits in the CAUSE register only when the interrupt
(exception) is triggered. This is the reason why checking
CAUSE register via splintr() in a while loop (to check if
another interrupt is triggered during interrupt) doesn't
work as expected on Giano.
I guess the author of the Giano simulator choose this design
because MIPS R4000 Microprocessor User's Manual says
"Cause register describes the cause of the most recent exception"
in the "Cause Register (13)" section. However I don't think it is
correct because the manual also says "bits in the interrupt register
are directly readable as bits of the Cause register", in section
15.3 "Asserting Interrupt".
I don't know whether the real FPGA eMIPS has the same design
as the Giano simulator , but for now I'd like to choose
'call only one handler per each interrupt' strategy, as
the original NetBSD/emips implementation. (It also just works)
Comments?
---
Index: emips/interrupt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/emips/emips/interrupt.c,v
retrieving revision 1.7
diff -u -p -d -r1.7 interrupt.c
--- emips/interrupt.c 9 Dec 2019 16:19:11 -0000 1.7
+++ emips/interrupt.c 10 Dec 2019 15:30:45 -0000
@@ -102,6 +102,19 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
curcpu()->ci_data.cpu_nintr++;
+#if 0
+ /*
+ * According to Giano simulator sources (Cpus/mips_cpu.cpp),
+ * interrupt register bits in CAUSE register are updated
+ * only when the exception is triggered. This means checking
+ * CAUSE register via splintr() in a while loop in this
+ * interrupt handler doesn't work as expected on Giano.
+ *
+ * I don't know whether the real FPGA eMIPS has the same
+ * design as the Giano simulator, but for now I'd like to
+ * choose 'call only one handler per each interrupt' strategy,
+ * as the original NetBSD/emips implementation.
+ */
while (ppl < (ipl = splintr(&ipending))) {
splx(ipl);
/* device interrupts */
@@ -110,6 +123,14 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
}
(void)splhigh();
}
+#else
+ ipl = splintr(&ipending);
+ __USE(ipl);
+ /* device interrupts */
+ if (ipending & MIPS_INT_MASK_5) {
+ (*platform.iointr)(status, pc, ipending);
+ }
+#endif
}
/*
---
Izumi Tsutsui
From: "Izumi Tsutsui" <tsutsui@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/45080 CVS commit: src/sys/arch/emips/emips
Date: Wed, 11 Dec 2019 16:16:13 +0000
Module Name: src
Committed By: tsutsui
Date: Wed Dec 11 16:16:13 UTC 2019
Modified Files:
src/sys/arch/emips/emips: interrupt.c
Log Message:
Fix a longstanding "freeze right after enabling interrupt" problem.
With this fix, finally NetBSD/emips on Giano is fully functional.
See PR/45080 for more details.
Should be pulled up to netbsd-9.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/emips/emips/interrupt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
State-Changed-From-To: analyzed->pending-pullups
State-Changed-By: tsutsui@NetBSD.org
State-Changed-When: Fri, 13 Dec 2019 10:22:30 +0000
State-Changed-Why:
[pullup-9 #549]
From: "Martin Husemann" <martin@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/45080 CVS commit: [netbsd-9] src/sys/arch/emips/emips
Date: Sat, 14 Dec 2019 12:22:43 +0000
Module Name: src
Committed By: martin
Date: Sat Dec 14 12:22:43 UTC 2019
Modified Files:
src/sys/arch/emips/emips [netbsd-9]: interrupt.c
Log Message:
Pull up following revision(s) (requested by tsutsui in ticket #549):
sys/arch/emips/emips/interrupt.c: revision 1.7
sys/arch/emips/emips/interrupt.c: revision 1.8
Fix incorrect argument order of cpu_intr(), slipped in rev 1.2.
Pointed out by maya@ in PR/45080.
Should be pulled up to netbsd-9.
-
Fix a longstanding "freeze right after enabling interrupt" problem.
With this fix, finally NetBSD/emips on Giano is fully functional.
See PR/45080 for more details.
Should be pulled up to netbsd-9.
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.6.22.1 src/sys/arch/emips/emips/interrupt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
State-Changed-From-To: pending-pullups->closed
State-Changed-By: tsutsui@NetBSD.org
State-Changed-When: Sat, 14 Dec 2019 13:33:30 +0000
State-Changed-Why:
Pulled up to netbsd-9.
I hope NetBSD/emips 9.0 will be the first functional release.
>Unformatted:
(Contact us)
$NetBSD: query-full-pr,v 1.45 2018/12/21 14:23:33 maya Exp $
$NetBSD: gnats_config.sh,v 1.9 2014/08/02 14:16:04 spz Exp $
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The NetBSD Foundation, Inc. ALL RIGHTS RESERVED.
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