NetBSD Problem Report #55138

From tsutsui@ceres.dti.ne.jp  Fri Apr  3 17:13:41 2020
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Date: Sat, 4 Apr 2020 02:13:31 +0900 (JST)
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
Reply-To: tsutsui@ceres.dti.ne.jp
To: gnats-bugs@NetBSD.org
Cc: tsutsui@ceres.dti.ne.jp
Subject: R5000 suspicious picache settings
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>Number:         55138
>Category:       port-mips
>Synopsis:       R5000 suspicious picache settings
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    port-mips-maintainer
>State:          closed
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Fri Apr 03 17:15:00 +0000 2020
>Closed-Date:    Sun Jun 21 07:11:44 +0000 2020
>Last-Modified:  Sun Jun 21 07:11:44 +0000 2020
>Originator:     Izumi Tsutsui
>Release:        NetBSD 9.0
>Organization:
>Environment:
System: NetBSD 9.0 
Architecture: mips
Machine: R5000 mips
>Description:
sys/arch/mips/mips/cache.c has the following code:
---
	case MIPS_R4600:
#ifdef ENABLE_MIPS_R4700
	case MIPS_R4700:
#endif
#ifndef ENABLE_MIPS_R3NKK
	case MIPS_R5000:
#endif
	case MIPS_RM5200:
primary_cache_is_2way:

 [...]

		switch (mci->mci_picache_line_size) {
		case 32:
			/* used internally by mipsNN_picache_sync_range */
			mco->mco_intern_icache_sync_range =
			    cache_r4k_icache_hit_inv_16;

			/* used internally by mipsNN_picache_sync_range_index */
			mco->mco_intern_icache_sync_range_index =
			    cache_r4k_icache_index_inv_16;
			break;

		default:
			panic("r5k picache line size %u",
			    mci->mci_picache_line_size);
		}
---

I.e. _16 cacheline functions (cache_r4k_icache_hit_inv_16
and cache_r4k_icache_index_inv_16) are specified in
mci_picache_line_size == 32 case for R5000.

In R4000 case actual cacheline size ops are specified.
---
		switch (mci->mci_picache_line_size) {
		case 16:
			mco->mco_icache_sync_range =
			    cache_r4k_icache_hit_inv_16;
			mco->mco_icache_sync_range_index =
			    cache_r4k_icache_index_inv_16;
			break;

		case 32:
			mco->mco_icache_sync_range =
			    cache_r4k_icache_hit_inv_32;
			mco->mco_icache_sync_range_index =
			    cache_r4k_icache_index_inv_32;
			break;
---

>How-To-Repeat:
Code inspection.

>Fix:
No idea if it's intentional design or bad copy and paste.

>Release-Note:

>Audit-Trail:
From: Nick Hudson <nick.hudson@gmx.co.uk>
To: gnats-bugs@netbsd.org, port-mips-maintainer@netbsd.org,
 gnats-admin@netbsd.org, netbsd-bugs@netbsd.org
Cc: 
Subject: Re: port-mips/55138: R5000 suspicious picache settings
Date: Sat, 4 Apr 2020 11:16:36 +0100

 On 03/04/2020 18:15, Izumi Tsutsui wrote:

 >> Synopsis:       R5000 suspicious picache settings

 I think this is bad copy&paste and have had it my mips tree for a while,
 but never dared to commit as I never really tested it.

 Nick

From: "Izumi Tsutsui" <tsutsui@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/55138 CVS commit: src/sys/arch/mips/mips
Date: Sun, 14 Jun 2020 14:16:50 +0000

 Module Name:	src
 Committed By:	tsutsui
 Date:		Sun Jun 14 14:16:49 UTC 2020

 Modified Files:
 	src/sys/arch/mips/mips: cache.c

 Log Message:
 Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache.  PR/55138

 Commented "I think this is bad copy&paste" from skrll@.
 No visible regression on Cobalt Qube 2700 (Rm5230) through
 whole installation using netbsd-9 based Cobalt RestoreCD/USB.


 To generate a diff of this commit:
 cvs rdiff -u -r1.66 -r1.67 src/sys/arch/mips/mips/cache.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

State-Changed-From-To: open->pending-pullups
State-Changed-By: tsutsui@NetBSD.org
State-Changed-When: Thu, 18 Jun 2020 17:37:45 +0000
State-Changed-Why:
[pullup-9 #964]


From: "Martin Husemann" <martin@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/55138 CVS commit: [netbsd-9] src/sys/arch/mips/mips
Date: Sat, 20 Jun 2020 16:35:02 +0000

 Module Name:	src
 Committed By:	martin
 Date:		Sat Jun 20 16:35:02 UTC 2020

 Modified Files:
 	src/sys/arch/mips/mips [netbsd-9]: cache.c

 Log Message:
 Pull up following revision(s) (requested by tsutsui in ticket #964):

 	sys/arch/mips/mips/cache.c: revision 1.67

 Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache.  PR/55138

 Commented "I think this is bad copy&paste" from skrll@.

 No visible regression on Cobalt Qube 2700 (Rm5230) through
 whole installation using netbsd-9 based Cobalt RestoreCD/USB.


 To generate a diff of this commit:
 cvs rdiff -u -r1.60 -r1.60.4.1 src/sys/arch/mips/mips/cache.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

State-Changed-From-To: pending-pullups->closed
State-Changed-By: tsutsui@NetBSD.org
State-Changed-When: Sun, 21 Jun 2020 07:11:44 +0000
State-Changed-Why:
Pullup complete.


>Unformatted:

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