NetBSD Problem Report #55653

From www@netbsd.org  Fri Sep 11 08:55:28 2020
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Date: Fri, 11 Sep 2020 08:55:27 +0000 (UTC)
From: daniel+netbsd@loffgren.org
Reply-To: daniel+netbsd@loffgren.org
To: gnats-bugs@NetBSD.org
Subject: Add SH7780 SCIF support
X-Send-Pr-Version: www-1.0

>Number:         55653
>Category:       port-sh3
>Synopsis:       Add SH7780 SCIF support
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    port-sh3-maintainer
>State:          open
>Class:          change-request
>Submitter-Id:   net
>Arrival-Date:   Fri Sep 11 09:00:00 +0000 2020
>Originator:     Daniel Loffgren
>Release:        NetBSD 9.99.71
>Organization:
>Environment:
Still being brought up, but it's a Renesas SH7723 eval board called "Wheat"
>Description:
I've been working (slowly) on bringing up an evaluation board that I got a hold of. In doing so I found that the SH7780 series of CPUs has a different base for the SCIF registers than the rest of the SH4 family.

I did quite a bit of digging to try and figure out the logic behind which CPUs have which bases. Unfortunately it appears to be specific to each series.        
Here is a breakdown of the SuperH family of CPUs into their series:         
    https://www.renesas.com/us/en/img/products/mcu-mpu/sh-roadmap-en.png    

My board has an SH7723, which is confusingly part of the SH7780 Series. I used the hardware manual to find the register locations. (Available here: https://www.renesas.com/us/en/doc/products/mpumcu/001/rej09b0158_sh7780hm.pdf )
Since this is part of the SH-4A family, I double checked the SH7450 series hardware manual (Available here: https://www.renesas.com/us/en/doc/products/mpumcu/doc/superh/r01uh0286ej_sh7450.pdf ) to see if it shared the same base; it doesn't. Since I happeend to have the info on-hand, I added both for posterity.                                   

I have verified that with this patch and a kernel built with SH7780 set, I get serial output on the SCIF0 port.                                        

I am not sure what CPUs use the current SH4_SCIF0_BASE value of 0xffe80000, so I've left it as the fallback if neither SH7780 or SH7450 are defined.
>How-To-Repeat:
Try to boot NetBSD/evbsh3 on an SH7780 series CPU
>Fix:
Index: sys/arch/sh3/include/scifreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sh3/include/scifreg.h,v
retrieving revision 1.11
diff -u -r1.11 scifreg.h
--- sys/arch/sh3/include/scifreg.h	28 May 2019 08:59:34 -0000	1.11
+++ sys/arch/sh3/include/scifreg.h	11 Sep 2020 08:41:18 -0000
@@ -36,7 +36,17 @@
 #define SH3_SCIF0_BASE	0xa4000150
 #define SH3_SCIF1_BASE	0xa4000140

-#define SH4_SCIF_BASE	0xffe80000
+#ifdef SH7780
+#define SH4_SCIF0_BASE	0xffe00000
+#define SH4_SCIF1_BASE	0xffe10000
+#elif SH7450
+#define SH4_SCIF0_BASE	0xffffc000
+#define SH4_SCIF1_BASE	0xffffc100
+#define SH4_SCIF2_BASE	0xffffc200
+#define SH4_SCIF3_BASE	0xffffc300
+#else /* SH4 Default */
+#define SH4_SCIF0_BASE	0xffe80000
+#endif

 #ifdef SH3

@@ -76,17 +86,17 @@
 #define SCIF_SPTR		0x20	/* seial port */
 #define SCIF_LSR		0x24	/* line status */

-#define	SHREG_SCSMR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR))
-#define	SHREG_SCBRR2  (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_BRR))
-#define	SHREG_SCSCR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR))
-#define	SHREG_SCFTDR2 (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_FTDR))
-#define	SHREG_SCSSR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR))
-#define	SHREG_SCFRDR2 (*(volatile uint8_t  *)(SH4_SCIF_BASE + SCIF_FRDR))
-#define	SHREG_SCFCR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR))
-#define	SHREG_SCFDR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR))
+#define	SHREG_SCSMR2  (*(volatile uint16_t *)(SH4_SCIF0_BASE + SCIF_SMR))
+#define	SHREG_SCBRR2  (*(volatile uint8_t  *)(SH4_SCIF0_BASE + SCIF_BRR))
+#define	SHREG_SCSCR2  (*(volatile uint16_t *)(SH4_SCIF0_BASE + SCIF_SCR))
+#define	SHREG_SCFTDR2 (*(volatile uint8_t  *)(SH4_SCIF0_BASE + SCIF_FTDR))
+#define	SHREG_SCSSR2  (*(volatile uint16_t *)(SH4_SCIF0_BASE + SCIF_SSR))
+#define	SHREG_SCFRDR2 (*(volatile uint8_t  *)(SH4_SCIF0_BASE + SCIF_FRDR))
+#define	SHREG_SCFCR2  (*(volatile uint16_t *)(SH4_SCIF0_BASE + SCIF_FCR))
+#define	SHREG_SCFDR2  (*(volatile uint16_t *)(SH4_SCIF0_BASE + SCIF_FDR))

-#define	SHREG_SCSPTR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR))
-#define	SHREG_SCLSR2  (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR))
+#define	SHREG_SCSPTR2 (*(volatile uint16_t *)(SH4_SCIF0_BASE + SCIF_SPTR))
+#define	SHREG_SCLSR2  (*(volatile uint16_t *)(SH4_SCIF0_BASE + SCIF_LSR))

 /* alias */
 #define	SHREG_SCSFDR2	SHREG_SCFTDR2

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