NetBSD Problem Report #57085
From www@netbsd.org Thu Nov 17 16:48:00 2022
Return-Path: <www@netbsd.org>
Received: from mail.netbsd.org (mail.netbsd.org [199.233.217.200])
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))
(Client CN "mail.NetBSD.org", Issuer "mail.NetBSD.org CA" (not verified))
by mollari.NetBSD.org (Postfix) with ESMTPS id B3AEE1A921F
for <gnats-bugs@gnats.NetBSD.org>; Thu, 17 Nov 2022 16:48:00 +0000 (UTC)
Message-Id: <20221117164756.BEA5D1A9239@mollari.NetBSD.org>
Date: Thu, 17 Nov 2022 16:47:56 +0000 (UTC)
From: jiaxun.yang@flygoat.com
Reply-To: jiaxun.yang@flygoat.com
To: gnats-bugs@NetBSD.org
Subject: evbmips/malta enhancements (patch)
X-Send-Pr-Version: www-1.0
>Number: 57085
>Category: port-evbmips
>Synopsis: evbmips/malta enhancements (patch)
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: port-evbmips-maintainer
>State: open
>Class: change-request
>Submitter-Id: net
>Arrival-Date: Thu Nov 17 16:50:00 +0000 2022
>Originator: Jiaxun Yang
>Release: CURRENT
>Organization:
>Environment:
N/A
>Description:
Some fixes and enhancements I did when I'm trying to bring up NetBSD evbmips-mipsel on malta CoreLV board.
Mainly:
1. Probe PCI I/O and MEM address spaces in gt driver instead of hardcode them, seems like my CoreLV have different address layout than default one.
2. Move all ISA related initialisation to pcib driver as we won't be able to tell if ISA is available before pcib attached
3. Enable PCI_NETBSD_CONFIGURE, on my CoreLV YAMON is leaving some BARs with mess.
4. Enable other device drivers that we may have.
5. As malta may come with system controller other than GT64120, leaving possibly to config with different system controllers though we may not implement it.
>How-To-Repeat:
Compile the kernel:
./build.sh -U -O ~/obj -j8 -m evbmips -a mipsel kernel=MALTA
Boot on Malta CoreLV.
Also tested with QEMU Malta:
qemu-system-mipsel -M malta -cpu 4Kc -kernel ~/obj/sys/arch/evbmips/compile/MALTA/netbsd -serial stdio
dmesg:
[ 1.0000000] MIPS32/64 params: cpu arch: 32
[ 1.0000000] MIPS32/64 params: TLB entries: 16
[ 1.0000000] MIPS32/64 params: Icache: line=16, total=2048, ways=2, sets=64, colors=0
[ 1.0000000] MIPS32/64 params: Dcache: line=16, total=2048, ways=2, sets=64, colors=0
[ 1.0000000] phys segment: 0x8000000 @ 0
[ 1.0000000] adding 0x791c000 @ 0x6e4000 to freelist 0
[ 1.0000000] Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
[ 1.0000000] 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017,
[ 1.0000000] 2018, 2019, 2020, 2021, 2022
[ 1.0000000] The NetBSD Foundation, Inc. All rights reserved.
[ 1.0000000] Copyright (c) 1982, 1986, 1989, 1991, 1993
[ 1.0000000] The Regents of the University of California. All rights reserved.
[ 1.0000000] NetBSD 9.99.106 (MALTA) #46: Thu Nov 17 16:45:59 GMT 2022
[ 1.0000000] flygoat@Kumiko.lan:/Users/flygoat/obj/sys/arch/evbmips/compile/MALTA
[ 1.0000000] MIPS Malta Evaluation Board
[ 1.0000000] total memory = 128 MB
[ 1.0000000] avail memory = 118 MB
[ 1.0000000] mainbus0 (root)
[ 1.0000000] cpu0 at mainbus0: 134.21MHz (hz cycles = 671088, delay divisor = 67)
[ 1.0000000] cpu0: MIPS 4Kc (0x18000) Rev. 0 with software emulated floating point
[ 1.0000000] cpu0: 16 TLB entries, 256MB max page size
[ 1.0000000] cpu0: 2KB/16B 2-way set-associative L1 instruction cache
[ 1.0000000] cpu0: 2KB/16B 2-way set-associative write-back L1 data cache
[ 1.0000000] gt0 at mainbus0 addr 0x1be00000
[ 1.0000000] PCI I/O window: 0x18000000 - 0x281fffff
[ 1.0000000] PCI MEM window0: 0x10000000 - 0x183fffff
[ 1.0000000] pci0 at gt0
[ 1.0000000] pchb0 at pci0 dev 0 function 0
[ 1.0000000] pchb0: Galileo Technology GT-64120A System Controller (rev. 0x10)
[ 1.0000000] pcib0 at pci0 dev 10 function 0
[ 1.0000000] pcib0: Intel 82371AB (PIIX4) PCI-ISA Bridge, (rev . 0x00)
[ 1.0000000] pciide0 at pci0 dev 10 function 1: Intel 82371AB (PIIX4) IDE Controller (rev. 0x00)
[ 1.0000000] pciide0: primary channel ignored (not responding; disabled or no drives?)
[ 1.0000000] pciide0: secondary channel ignored (other hardware responding at addresses)
[ 1.0000000] uhci0 at pci0 dev 10 function 2: Intel 82371AB (PIIX4) USB Host Controller (rev. 0x01)
[ 1.0000000] uhci0: interrupting at isa irq 11
[ 1.0000000] usb0 at uhci0: USB revision 1.0
[ 1.0000000] Intel 82371AB (PIIX4) Power Management Controller (miscellaneous bridge, revision 0x03) at pci0 dev 10 function 3 not configured
[ 1.0000000] pcn0 at pci0 dev 11 function 0: AMD PCnet-PCI Ethernet
[ 1.0000000] pcn0: Am79c970A PCnet-PCI II rev 0, Ethernet address ff:ff:ff:ff:ff:ff
[ 1.0000000] pcn0: interrupting at isa irq 10
[ 1.0000000] pcn0: 10base5, 10base5-FDX, 10baseT, 10baseT-FDX, auto, auto-FDX
[ 1.0000000] Cirrus Logic CL-GD5446 (VGA display) at pci0 dev 18 function 0 not configured
[ 1.0000000] isa0 at pcib0
[ 1.0000000] com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, 16-byte FIFO
[ 1.0000000] com0: console
[ 1.0000000] com1 at isa0 port 0x2f8-0x2ff irq 3: ns16550a, 16-byte FIFO
[ 1.0000000] pckbc0 at isa0 port 0x60-0x64
[ 1.0000000] pckbd0 at pckbc0 (kbd slot)
[ 1.0000000] pckbc0: using irq 1 for kbd slot
[ 1.0000000] wskbd0 at pckbd0 (mux ignored)
[ 1.0000000] pms0 at pckbc0 (aux slot)
[ 1.0000000] pckbc0: using irq 12 for aux slot
[ 1.0000000] wsmouse0 at pms0 (mux ignored)
[ 1.0000000] mcclock0 at isa0 port 0x70-0x71: mc146818 compatible time-of-day clock
[ 1.0300040] uhub0 at usb0: NetBSD (0x0000) UHCI root hub (0x0000), class 9/0, rev 1.00/1.00, addr 1
[ 1.0411575] WARNING: system needs entropy for security; see entropy(7)
[ 1.5515695] WARNING: 2 errors while detecting hardware; check system log.
>Fix:
PATCH:
---
sys/arch/evbmips/conf/MALTA | 18 +-
sys/arch/evbmips/conf/files.malta | 2 +-
sys/arch/evbmips/include/pci_machdep.h | 2 +
sys/arch/evbmips/malta/autoconf.h | 4 +-
sys/arch/evbmips/malta/dev/gt.c | 159 ++++++++++++++----
sys/arch/evbmips/malta/dev/gtreg.h | 15 +-
sys/arch/evbmips/malta/dev/gtvar.h | 15 --
sys/arch/evbmips/malta/dev/mainbus.c | 55 +-----
sys/arch/evbmips/malta/machdep.c | 37 +---
sys/arch/evbmips/malta/malta_bus_mem.c | 34 +---
sys/arch/evbmips/malta/malta_intr.c | 2 +-
sys/arch/evbmips/malta/maltareg.h | 17 +-
sys/arch/evbmips/malta/maltavar.h | 15 +-
.../malta/{malta_bus_io.c => pci/pci_io_bs.c} | 15 +-
sys/arch/evbmips/malta/pci/pcib.c | 60 +++++++
sys/arch/mips/include/pci_machdep.h | 7 +
16 files changed, 252 insertions(+), 205 deletions(-)
delete mode 100644 sys/arch/evbmips/malta/dev/gtvar.h
rename sys/arch/evbmips/malta/{malta_bus_io.c => pci/pci_io_bs.c} (79%)
diff --git a/sys/arch/evbmips/conf/MALTA b/sys/arch/evbmips/conf/MALTA
index 2d37938186ed..c5ba7d6492de 100644
--- a/sys/arch/evbmips/conf/MALTA
+++ b/sys/arch/evbmips/conf/MALTA
@@ -101,7 +101,7 @@ options INET # Internet protocols
# These options enable verbose messages for several subsystems.
# Warning, these may compile large string tables into the kernel!
-#options PCI_NETBSD_CONFIGURE # NetBSD configures the PCI bus
+options PCI_NETBSD_CONFIGURE # NetBSD configures the PCI bus
options PCIVERBOSE # verbose PCI device autoconfig messages
#options PCI_CONFIG_DUMP # verbosely dump PCI config space
#options SCSIVERBOSE # human readable SCSI error messages
@@ -121,7 +121,7 @@ config netbsd root on ? type ?
mainbus0 at root
cpu0 at mainbus?
-gt0 at mainbus?
+gt0 at mainbus? addr 0x1be00000
#com2 at mainbus? # CBUS UART (ugh, 64 bit register spacing)
@@ -142,13 +142,13 @@ com1 at isa? port 0x2f8 irq 3
#fd* at fdc? drive ?
# wscons
-#vga* at pci? dev ? function ?
-#wsdisplay* at vga? console ?
-#pckbc* at isa? # PC keyboard controller
-#pckbd* at pckbc? # PC keyboard (kbd port)
-#pms* at pckbc? # PS/2-style mouse (aux port)
-#wskbd* at pckbd?
-#wsmouse* at pms?
+vga* at pci? dev ? function ?
+wsdisplay* at vga? console ?
+pckbc* at isa? # PC keyboard controller
+pckbd* at pckbc? # PC keyboard (kbd port)
+pms* at pckbc? # PS/2-style mouse (aux port)
+wskbd* at pckbd?
+wsmouse* at pms?
# PCI SCSI controllers
#adv* at pci? dev ? function ? # AdvanSys 1200[A,B], 9xx[U,UA]
diff --git a/sys/arch/evbmips/conf/files.malta b/sys/arch/evbmips/conf/files.malta
index d81af4b46cb2..1f7becd2d8ba 100644
--- a/sys/arch/evbmips/conf/files.malta
+++ b/sys/arch/evbmips/conf/files.malta
@@ -1,6 +1,5 @@
# $NetBSD: files.malta,v 1.20 2015/06/07 21:05:33 matt Exp $
-file arch/evbmips/malta/malta_bus_io.c
file arch/evbmips/malta/malta_bus_mem.c
file arch/evbmips/malta/malta_dma.c
file arch/evbmips/malta/malta_intr.c
@@ -65,6 +64,7 @@ attach gt at mainbus
file arch/evbmips/malta/dev/gt.c gt # XXX should be in arch/mips/galileo ?
file arch/evbmips/malta/pci/pci_machdep.c pci
+file arch/evbmips/malta/pci/pci_io_bs.c pci
file arch/mips/pci/pciide_machdep.c pciide_common
device pchb
diff --git a/sys/arch/evbmips/include/pci_machdep.h b/sys/arch/evbmips/include/pci_machdep.h
index 810c63ba0d3f..3a9f53c1af74 100644
--- a/sys/arch/evbmips/include/pci_machdep.h
+++ b/sys/arch/evbmips/include/pci_machdep.h
@@ -10,4 +10,6 @@
#define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
#endif
+#define __HAVE_PCI_CONF_HOOK
+
#include <mips/pci_machdep.h>
diff --git a/sys/arch/evbmips/malta/autoconf.h b/sys/arch/evbmips/malta/autoconf.h
index a4b8f25ec466..fc51cea7562e 100644
--- a/sys/arch/evbmips/malta/autoconf.h
+++ b/sys/arch/evbmips/malta/autoconf.h
@@ -41,6 +41,6 @@ struct mainbus_attach_args {
const char *ma_name;
unsigned long ma_addr;
int ma_intr;
- bus_space_tag_t ma_iot;
- bus_space_handle_t ma_ioh;
+ bus_space_tag_t ma_memt;
+ bus_space_handle_t ma_memh;
};
diff --git a/sys/arch/evbmips/malta/dev/gt.c b/sys/arch/evbmips/malta/dev/gt.c
index 15e9f90786f3..4f48bd558f55 100644
--- a/sys/arch/evbmips/malta/dev/gt.c
+++ b/sys/arch/evbmips/malta/dev/gt.c
@@ -38,27 +38,36 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.17 2021/08/07 16:18:51 thorpej Exp $");
+#include "opt_pci.h"
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <dev/pci/pcivar.h>
+#include <dev/pci/pciconf.h>
#include <mips/cpuregs.h>
+#include <evbmips/malta/autoconf.h>
#include <evbmips/malta/maltareg.h>
#include <evbmips/malta/maltavar.h>
#include <evbmips/malta/dev/gtreg.h>
-#include <evbmips/malta/dev/gtvar.h>
+
+#include <mips/cache.h>
#include "pci.h"
-/*
- * Galileo systems (so far) are always single-processor, so this is sufficient.
- */
-#define PCI_CONF_LOCK(s) (s) = splhigh()
-#define PCI_CONF_UNLOCK(s) splx((s))
+#define PCI_IO_RESERVED_SIZE 0x1000
+
+struct gt_softc {
+ device_t sc_dev;
+ kmutex_t sc_pci_lock;
+
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
static void gt_attach_hook(device_t, device_t, struct pcibus_attach_args *);
static int gt_bus_maxdevs(void *, int);
@@ -66,19 +75,8 @@ static pcitag_t gt_make_tag(void *, int, int, int);
static void gt_decompose_tag(void *, pcitag_t, int *, int *, int *);
static pcireg_t gt_conf_read(void *, pcitag_t, int);
static void gt_conf_write(void *, pcitag_t, int, pcireg_t);
+static int gt_conf_hook(void *, int, int, int, pcireg_t);
-void
-gt_pci_init(pci_chipset_tag_t pc, struct gt_config *mcp)
-{
-
- pc->pc_conf_v = mcp;
- pc->pc_attach_hook = gt_attach_hook;
- pc->pc_bus_maxdevs = gt_bus_maxdevs;
- pc->pc_make_tag = gt_make_tag;
- pc->pc_decompose_tag = gt_decompose_tag;
- pc->pc_conf_read = gt_conf_read;
- pc->pc_conf_write = gt_conf_write;
-}
static void
gt_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba)
@@ -91,7 +89,7 @@ static int gt_match(device_t, cfdata_t, void *);
static void gt_attach(device_t, device_t, void *);
static int gt_print(void *aux, const char *pnp);
-CFATTACH_DECL_NEW(gt, 0,
+CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc),
gt_match, gt_attach, NULL, NULL);
static int
@@ -103,16 +101,86 @@ gt_match(device_t parent, cfdata_t match, void *aux)
static void
gt_attach(device_t parent, device_t self, void *aux)
{
+ struct mainbus_attach_args *ma = aux;
struct malta_config *mcp = &malta_configuration;
- struct pcibus_attach_args pba;
-
- printf("\n");
+ struct gt_softc *sc = device_private(self);
+ struct mips_pci_chipset *pc = &mcp->mc_pc;
+ bus_addr_t isd_addr;
+ bus_size_t pci_io_size;
+ bus_addr_t pci_mem_start;
+ bus_size_t pci_mem_size;
+
+ sc->sc_dev = self;
+ aprint_normal("\n");
+
+ sc->sc_bst = ma->ma_memt;
+ if (bus_space_map(sc->sc_bst, ma->ma_addr, 0x1000,
+ 0, &sc->sc_bsh)) {
+ aprint_error(": unable to map GT64120 registers\n");
+ return;
+ }
+
+ isd_addr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_ISD);
+ isd_addr <<= 21;
+ isd_addr &= 0xffe00000;
+
+ if (isd_addr != ma->ma_addr) {
+ /* This is not fatal */
+ aprint_error("ISD addr mismatch, window: %#"PRIxBUSADDR
+ " ma: %#"PRIxBUSADDR"\n",
+ isd_addr, (bus_addr_t)ma->ma_addr);
+ }
+
+ mcp->mc_pci_io_start = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI0IOLD) << 21;
+ pci_io_size = ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI0IOLD) + 1) - \
+ (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI0IOHD) & 0x7f)) << 21;
+ mcp->mc_pci_io_end = mcp->mc_pci_io_start + pci_io_size - 1;
+ aprint_normal("PCI I/O window: %#"PRIxBUSADDR" - %#"PRIxBUSADDR"\n",
+ mcp->mc_pci_io_start, mcp->mc_pci_io_end);
+
+ pci_mem_start = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI0M0LD) << 21;
+ pci_mem_size = ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI0M0LD) + 1) - \
+ (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI0M0HD) & 0x7f)) << 21;
+ aprint_normal("PCI MEM window0: %#"PRIxBUSADDR" - %#"PRIxBUSADDR"\n",
+ pci_mem_start,
+ (bus_addr_t)(pci_mem_start + pci_mem_size - 1));
+
+ /* Don't mess with window 1 as it may overlap with ISD */
+
+ malta_pci_bus_io_init(&mcp->mc_pci_iot, mcp);
+
+ mutex_init(&sc->sc_pci_lock, MUTEX_DEFAULT, IPL_HIGH);
+
+ mcp->mc_controller_sc = sc;
+ pc->pc_conf_v = mcp;
+ pc->pc_attach_hook = gt_attach_hook;
+ pc->pc_bus_maxdevs = gt_bus_maxdevs;
+ pc->pc_make_tag = gt_make_tag;
+ pc->pc_decompose_tag = gt_decompose_tag;
+ pc->pc_conf_read = gt_conf_read;
+ pc->pc_conf_write = gt_conf_write;
+ pc->pc_conf_hook = gt_conf_hook;
#if NPCI > 0
+#ifdef PCI_NETBSD_CONFIGURE
+ struct mips_cache_info * const mci = &mips_cache_info;
+ struct pciconf_resources *pcires = pciconf_resource_init();
+
+ pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, PCI_IO_RESERVED_SIZE,
+ pci_io_size - PCI_IO_RESERVED_SIZE);
+ pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, pci_mem_start, pci_mem_size);
+
+
+ pci_configure_bus(pc, pcires, 0, mci->mci_dcache_align);
+ pciconf_resource_fini(pcires);
+#endif /* PCI_NETBSD_CONFIGURE */
+
+ struct pcibus_attach_args pba;
+
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
- pba.pba_iot = &mcp->mc_iot;
+ pba.pba_iot = &mcp->mc_pci_iot;
pba.pba_memt = &mcp->mc_memt;
pba.pba_dmat = &mcp->mc_pci_dmat; /* pci_bus_dma_tag */
pba.pba_dmat64 = NULL;
@@ -162,7 +230,9 @@ static pcireg_t
gt_conf_read(void *v, pcitag_t tag, int offset)
{
pcireg_t data;
- int bus, dev, func, s;
+ struct malta_config *mcp = v;
+ struct gt_softc *sc = mcp->mc_controller_sc;
+ int bus, dev, func;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return ((pcireg_t) -1);
@@ -177,19 +247,22 @@ gt_conf_read(void *v, pcitag_t tag, int offset)
if (bus > 0)
return ((pcireg_t) -1);
- PCI_CONF_LOCK(s);
+ mutex_enter(&sc->sc_pci_lock);
/* Clear cause register bits. */
- GT_REGVAL(GT_INTR_CAUSE) = 0;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_INTR_CAUSE, 0);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI0_CFG_ADDR,
+ (1 << 31) | tag | offset);
- GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
- data = GT_REGVAL(GT_PCI0_CFG_DATA);
+ data = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI0_CFG_DATA);
/* Check for master abort. */
- if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0))
+ if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_INTR_CAUSE) &
+ (GTIC_MASABORT0 | GTIC_TARABORT0)) {
data = (pcireg_t) -1;
+ }
- PCI_CONF_UNLOCK(s);
+ mutex_exit(&sc->sc_pci_lock);
return (data);
}
@@ -197,7 +270,9 @@ gt_conf_read(void *v, pcitag_t tag, int offset)
static void
gt_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
{
- int bus, dev, func, s;
+ int bus, dev, func;
+ struct malta_config *mcp = v;
+ struct gt_softc *sc = mcp->mc_controller_sc;
if ((unsigned int)offset >= PCI_CONF_SIZE)
return;
@@ -212,13 +287,25 @@ gt_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
if (bus > 0)
return;
- PCI_CONF_LOCK(s);
+ mutex_enter(&sc->sc_pci_lock);
/* Clear cause register bits. */
- GT_REGVAL(GT_INTR_CAUSE) = 0;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_INTR_CAUSE, 0);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI0_CFG_ADDR,
+ (1 << 31) | tag | offset);
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI0_CFG_DATA, data);
- GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
- GT_REGVAL(GT_PCI0_CFG_DATA) = data;
+ mutex_exit(&sc->sc_pci_lock);
+}
+
+static int
+gt_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
+{
+ /* Leave host bridge alone */
+ if (bus == 0 && dev == 0 && func == 0) {
+ return 0;
+ }
- PCI_CONF_UNLOCK(s);
+ return PCI_CONF_DEFAULT;
}
diff --git a/sys/arch/evbmips/malta/dev/gtreg.h b/sys/arch/evbmips/malta/dev/gtreg.h
index 50e66a0d3adf..f572116b4a6f 100644
--- a/sys/arch/evbmips/malta/dev/gtreg.h
+++ b/sys/arch/evbmips/malta/dev/gtreg.h
@@ -7,7 +7,20 @@
#define GT_CPU_INT 0x000
#define GT_MULTIGT 0x120
-/* CPU Address Decode Register Map */
+/* CPU Address Decode. */
+#define GT_SCS10LD 0x008
+#define GT_SCS10HD 0x010
+#define GT_SCS32LD 0x018
+#define GT_SCS32HD 0x020
+#define GT_CS20LD 0x028
+#define GT_CS20HD 0x030
+#define GT_CS3BOOTLD 0x038
+#define GT_CS3BOOTHD 0x040
+#define GT_PCI0IOLD 0x048
+#define GT_PCI0IOHD 0x050
+#define GT_PCI0M0LD 0x058
+#define GT_PCI0M0HD 0x060
+#define GT_ISD 0x068
/* CPU Error Report Register Map */
diff --git a/sys/arch/evbmips/malta/dev/gtvar.h b/sys/arch/evbmips/malta/dev/gtvar.h
deleted file mode 100644
index 17c56e2af1cf..000000000000
--- a/sys/arch/evbmips/malta/dev/gtvar.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* $NetBSD: gtvar.h,v 1.1 2002/03/07 14:44:05 simonb Exp $ */
-
-#ifndef _MALTA_GTVAR_H_
-#define _MALTA_GTVAR_H_
-
-#include <dev/pci/pcivar.h>
-
-struct gt_config {
- int foo;
-};
-
-#ifdef _KERNEL
-void gt_pci_init(pci_chipset_tag_t, struct gt_config *);
-#endif
-#endif /* !_MALTA_GTVAR_H_ */
diff --git a/sys/arch/evbmips/malta/dev/mainbus.c b/sys/arch/evbmips/malta/dev/mainbus.c
index e397c0e5980b..0f1d89ba54d2 100644
--- a/sys/arch/evbmips/malta/dev/mainbus.c
+++ b/sys/arch/evbmips/malta/dev/mainbus.c
@@ -38,19 +38,9 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.17 2021/08/07 16:18:51 thorpej Exp $");
-#include "opt_pci.h"
-
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
-#if defined(PCI_NETBSD_CONFIGURE)
-#include <sys/malloc.h>
-#endif
-
-#include <dev/pci/pcivar.h>
-#if defined(PCI_NETBSD_CONFIGURE)
-#include <dev/pci/pciconf.h>
-#endif
#include <mips/cache.h>
#include <mips/cpuregs.h>
@@ -59,10 +49,6 @@ __KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.17 2021/08/07 16:18:51 thorpej Exp $")
#include <evbmips/malta/maltareg.h>
#include <evbmips/malta/maltavar.h>
-#if defined(PCI_NETBSD_ENABLE_IDE)
-#include <dev/pci/pciide_piix_reg.h>
-#endif /* PCI_NETBSD_ENABLE_IDE */
-
#include "locators.h"
#include "pci.h"
@@ -92,12 +78,6 @@ const struct mainbusdev mainbusdevs[] = {
{ NULL, 0, 0 },
};
-#define PCI_IO_START 0x00001000
-#define PCI_IO_END 0x0000efff
-#define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
-
-#define PCI_MEM_START MALTA_PCIMEM1_BASE
-#define PCI_MEM_SIZE MALTA_PCIMEM1_SIZE
static int
mainbus_match(device_t parent, cfdata_t match, void *aux)
@@ -114,46 +94,13 @@ mainbus_attach(device_t parent, device_t self, void *aux)
{
struct mainbus_attach_args ma;
const struct mainbusdev *md;
-#if defined(PCI_NETBSD_ENABLE_IDE) || defined(PCI_NETBSD_CONFIGURE)
struct malta_config *mcp = &malta_configuration;
- pci_chipset_tag_t pc = &mcp->mc_pc;
-#endif
mainbus_found = true;
printf("\n");
-#if defined(PCI_NETBSD_CONFIGURE)
- struct mips_cache_info * const mci = &mips_cache_info;
- struct pciconf_resources *pcires = pciconf_resource_init();
-
- pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
- PCI_IO_START, PCI_IO_SIZE);
- pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
- PCI_MEM_START, PCI_MEM_SIZE);
-
- pci_configure_bus(pc, pcires, 0, mci->mci_dcache_align);
- pciconf_resource_fini(pcires);
-#endif /* PCI_NETBSD_CONFIGURE */
-
-#if defined(PCI_NETBSD_ENABLE_IDE)
- /*
- * Perhaps PMON has not enabled the IDE controller. Easy to
- * fix -- just set the ENABLE bits for each channel in the
- * IDETIM register. Just clear all the bits for the channel
- * except for the ENABLE bits -- the `pciide' driver will
- * properly configure it later.
- */
- pcireg_t idetim = 0;
- if (PCI_NETBSD_ENABLE_IDE & 0x01)
- idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
- if (PCI_NETBSD_ENABLE_IDE & 0x02)
- idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
-
- /* pciide0 is pci device 10, function 1 */
- pcitag_t idetag = pci_make_tag(pc, 0, 10, 1);
- pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
-#endif
for (md = mainbusdevs; md->md_name != NULL; md++) {
+ ma.ma_memt = &mcp->mc_memt;
ma.ma_name = md->md_name;
ma.ma_addr = md->md_addr;
ma.ma_intr = md->md_intr;
diff --git a/sys/arch/evbmips/malta/machdep.c b/sys/arch/evbmips/malta/machdep.c
index e82ae89675eb..6a35f0925e73 100644
--- a/sys/arch/evbmips/malta/machdep.c
+++ b/sys/arch/evbmips/malta/machdep.c
@@ -113,13 +113,6 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.46 2016/12/22 14:47:57 cherry Exp $");
#include <evbmips/malta/maltareg.h>
#include <evbmips/malta/maltavar.h>
-#include "com.h"
-#if NCOM > 0
-#include <dev/ic/comreg.h>
-#include <dev/ic/comvar.h>
-
-int comcnrate = 38400; /* XXX should be config option */
-#endif /* NCOM > 0 */
#define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
@@ -147,9 +140,7 @@ mach_init(int argc, char **argv, yamon_env_var *envp, u_long memsize)
{
struct malta_config *mcp = &malta_configuration;
uint8_t * const brkres = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_BRKRES);
- bus_space_handle_t sh;
void *kernend;
- int freqok;
extern char edata[], end[];
@@ -188,37 +179,11 @@ mach_init(int argc, char **argv, yamon_env_var *envp, u_long memsize)
/*
* Use YAMON's CPU frequency if available.
*/
- freqok = yamon_setcpufreq(1);
+ mcp->freqok = yamon_setcpufreq(1);
- gt_pci_init(&mcp->mc_pc, &mcp->mc_gt);
- malta_bus_io_init(&mcp->mc_iot, mcp);
malta_bus_mem_init(&mcp->mc_memt, mcp);
malta_dma_init(mcp);
- /*
- * Calibrate the timer if YAMON failed to tell us.
- */
- if (!freqok) {
- bus_space_map(&mcp->mc_iot, MALTA_RTCADR, 2, 0, &sh);
- malta_cal_timer(&mcp->mc_iot, sh);
- bus_space_unmap(&mcp->mc_iot, sh, 2);
- }
-
-#if NCOM > 0
- /*
- * Delay to allow firmware putchars to complete.
- * FIFO depth * character time.
- * character time = (1000000 / (defaultrate / 10))
- */
- delay(160000000 / comcnrate);
- if (comcnattach(&mcp->mc_iot, MALTA_UART0ADR, comcnrate,
- COM_FREQ, COM_TYPE_NORMAL,
- (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) != 0)
- panic("malta: unable to initialize serial console");
-#else
- panic("malta: not configured to use serial console");
-#endif /* NCOM > 0 */
-
mem_clusters[0].start = 0;
mem_clusters[0].size = ctob(physmem);
mem_cluster_cnt = 1;
diff --git a/sys/arch/evbmips/malta/malta_bus_mem.c b/sys/arch/evbmips/malta/malta_bus_mem.c
index 6b65e4bda8e0..fc60c2822f5f 100644
--- a/sys/arch/evbmips/malta/malta_bus_mem.c
+++ b/sys/arch/evbmips/malta/malta_bus_mem.c
@@ -47,34 +47,10 @@ __KERNEL_RCSID(0, "$NetBSD: malta_bus_mem.c,v 1.7 2008/04/28 20:23:17 martin Exp
#define CHIP_EX_MALLOC_SAFE(v) (((struct malta_config *)(v))->mc_mallocsafe)
#define CHIP_EXTENT(v) (((struct malta_config *)(v))->mc_mem_ex)
-#if 1
-/*
- * There are actually 2 PCILO memory windows, but they are configured
- * as one contiguous PCI memory space.
- */
-
-/* MEM region 1 */
-#define CHIP_W1_BUS_START(v) MALTA_PCIMEM1_BASE
-#define CHIP_W1_BUS_END(v) MALTA_PCIMEM1_SIZE + \
- MALTA_PCIMEM2_SIZE
-#define CHIP_W1_SYS_START(v) ((u_long)MALTA_PCIMEM1_BASE)
-#define CHIP_W1_SYS_END(v) ((u_long)MALTA_PCIMEM1_BASE + \
- CHIP_W1_BUS_END(v))
-#else
-
-/* MEM region 1 */
-#define CHIP_W1_BUS_START(v) MALTA_PCIMEM1_BASE
-#define CHIP_W1_BUS_END(v) MALTA_PCIMEM1_SIZE
-#define CHIP_W1_SYS_START(v) ((u_long)MALTA_PCIMEM1_BASE)
-#define CHIP_W1_SYS_END(v) ((u_long)MALTA_PCIMEM1_BASE + \
- CHIP_W1_BUS_END(v))
-
-/* MEM region 2 */
-#define CHIP_W2_BUS_START(v) MALTA_PCIMEM2_BASE
-#define CHIP_W2_BUS_END(v) MALTA_PCIMEM2_SIZE
-#define CHIP_W2_SYS_START(v) ((u_long)MALTA_PCIMEM2_BASE)
-#define CHIP_W2_SYS_END(v) ((u_long)MALTA_PCIMEM2_BASE + \
- CHIP_W2_BUS_END(v))
-#endif
+/* All possible MMIO regions */
+#define CHIP_W1_BUS_START(v) 0x08000000
+#define CHIP_W1_BUS_END(v) 0x3fffffff
+#define CHIP_W1_SYS_START(v) 0x08000000
+#define CHIP_W1_SYS_END(v) 0x3fffffff
#include <mips/mips/bus_space_alignstride_chipdep.c>
diff --git a/sys/arch/evbmips/malta/malta_intr.c b/sys/arch/evbmips/malta/malta_intr.c
index 887ab5f5da04..c118254553e1 100644
--- a/sys/arch/evbmips/malta/malta_intr.c
+++ b/sys/arch/evbmips/malta/malta_intr.c
@@ -274,7 +274,7 @@ evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
* YAMON configures pa_intrline correctly (so far), so we trust it to DTRT
* in the future...
*/
-#undef YAMON_IRQ_MAP_BAD
+#define YAMON_IRQ_MAP_BAD
/*
* PCI interrupt support
diff --git a/sys/arch/evbmips/malta/maltareg.h b/sys/arch/evbmips/malta/maltareg.h
index 509e90603bae..1cfd49799035 100644
--- a/sys/arch/evbmips/malta/maltareg.h
+++ b/sys/arch/evbmips/malta/maltareg.h
@@ -39,7 +39,8 @@
Memory Map
0000.0000 * 128MB Typically SDRAM (on Core Board)
- 0800.0000 * 256MB Typically PCI
+ 0800.0000 * 256MB Typically SDRAM CS2 (on Core Board)
+ 1000.0000 * 128MB Typically PCI
1800.0000 * 62MB Typically PCI
1be0.0000 * 2MB Typically System controller's internal registers
1c00.0000 * 32MB Typically not used
@@ -58,6 +59,8 @@
1fd0.0000 * 3MB Typically System Controller specific
* depends on implementation of the Core Board and of software
+ * Note: For GT64120, YAMON is not following this MAP, we have to
+ * read from GT internal registers instead.
*/
/*
@@ -95,14 +98,14 @@
#define MALTA_SYSTEMRAM_BASE 0x00000000 /* System RAM: */
#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */
-#define MALTA_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */
+#define MALTA_PCIMEM1_BASE 0x10000000 /* PCI 1 memory: */
#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */
-#define MALTA_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */
-#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */
+#define MALTA_PCIIO_BASE 0x18000000 /* PCI IO memory */
+#define MALTA_PCIIO_SIZE 0x00200000 /* 2 MByte */
-#define MALTA_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */
-#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */
+#define MALTA_PCIMEM2_BASE 0x18200000 /* PCI 2 memory: */
+#define MALTA_PCIMEM2_SIZE 0x0be00000 /* 128 MByte */
#define MALTA_CORECTRL_BASE 0x1be00000 /* Core control: */
#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */
@@ -202,7 +205,7 @@
/* PCI definitions */
#define MALTA_SOUTHBRIDGE_INTR 0
-#define MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE
+#define MALTA_PCI0_IO_BASE MALTA_PCIIO_BASE
#define MALTA_PCI0_ADDR( addr ) (MALTA_PCI0_IO_BASE + (addr))
#define MALTA_RTCADR 0x70 // MALTA_PCI_IO_ADDR8(0x70)
diff --git a/sys/arch/evbmips/malta/maltavar.h b/sys/arch/evbmips/malta/maltavar.h
index f0b987cae646..37b091790f54 100644
--- a/sys/arch/evbmips/malta/maltavar.h
+++ b/sys/arch/evbmips/malta/maltavar.h
@@ -33,33 +33,34 @@
#include <dev/pci/pcivar.h>
#include <dev/isa/isavar.h>
-#include <evbmips/malta/dev/gtvar.h>
-
struct malta_config {
- struct gt_config mc_gt;
+ void *mc_controller_sc;
- struct mips_bus_space mc_iot;
struct mips_bus_space mc_memt;
+ struct mips_bus_space mc_pci_iot;
struct mips_bus_dma_tag mc_pci_dmat;
struct mips_pci_chipset mc_pc;
struct mips_isa_chipset mc_ic;
- struct extent *mc_io_ex;
struct extent *mc_mem_ex;
+ struct extent *mc_pci_io_ex;
+
+ bus_addr_t mc_pci_io_start;
+ bus_addr_t mc_pci_io_end;
int mc_mallocsafe;
+ int freqok;
};
#ifdef _KERNEL
extern struct malta_config malta_configuration;
-void malta_bus_io_init(bus_space_tag_t, void *);
void malta_bus_mem_init(bus_space_tag_t, void *);
void malta_cal_timer(bus_space_tag_t, bus_space_handle_t);
void malta_dma_init(struct malta_config *);
int malta_get_ethaddr(int, u_int8_t *);
void malta_intr_init(struct malta_config *);
-void malta_pci_init(pci_chipset_tag_t, struct malta_config *);
+void malta_pci_bus_io_init(bus_space_tag_t, void *);
#endif /* _KERNEL */
diff --git a/sys/arch/evbmips/malta/malta_bus_io.c b/sys/arch/evbmips/malta/pci/pci_io_bs.c
similarity index 79%
rename from sys/arch/evbmips/malta/malta_bus_io.c
rename to sys/arch/evbmips/malta/pci/pci_io_bs.c
index 97f041850c42..827696f0d35f 100644
--- a/sys/arch/evbmips/malta/malta_bus_io.c
+++ b/sys/arch/evbmips/malta/pci/pci_io_bs.c
@@ -41,17 +41,18 @@ __KERNEL_RCSID(0, "$NetBSD: malta_bus_io.c,v 1.6 2008/04/28 20:23:17 martin Exp
#include <evbmips/malta/maltareg.h>
#include <evbmips/malta/maltavar.h>
-#define CHIP malta
+#define CHIP malta_pci
#define CHIP_IO /* defined */
#define CHIP_EX_MALLOC_SAFE(v) (((struct malta_config *)(v))->mc_mallocsafe)
-#define CHIP_EXTENT(v) (((struct malta_config *)(v))->mc_io_ex)
+#define CHIP_EXTENT(v) (((struct malta_config *)(v))->mc_pci_io_ex)
/* IO region 1 */
-#define CHIP_W1_BUS_START(v) 0x00000000UL
-#define CHIP_W1_BUS_END(v) MALTA_PCIMEM3_SIZE
-#define CHIP_W1_SYS_START(v) ((u_long)MALTA_PCIMEM3_BASE)
-#define CHIP_W1_SYS_END(v) ((u_long)MALTA_PCIMEM3_BASE + \
- CHIP_W1_BUS_END(v))
+#define CHIP_W1_BUS_START(v) 0x00000000
+#define CHIP_W1_BUS_END(v) (MALTA_PCIIO_SIZE -1)
+// #define CHIP_W1_BUS_END(v) (((struct malta_config *)(v))->mc_pci_io_end -
+// ((struct malta_config *)(v))->mc_pci_io_start)
+#define CHIP_W1_SYS_START(v) (((struct malta_config *)(v))->mc_pci_io_start)
+#define CHIP_W1_SYS_END(v) (((struct malta_config *)(v))->mc_pci_io_end)
#include <mips/mips/bus_space_alignstride_chipdep.c>
diff --git a/sys/arch/evbmips/malta/pci/pcib.c b/sys/arch/evbmips/malta/pci/pcib.c
index 32ba04c68e10..ec774e3fe1cf 100644
--- a/sys/arch/evbmips/malta/pci/pcib.c
+++ b/sys/arch/evbmips/malta/pci/pcib.c
@@ -38,11 +38,14 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.24 2022/01/22 15:10:31 skrll Exp $");
+#include "opt_pci.h"
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/kmem.h>
+#include <sys/termios.h>
#include <uvm/uvm_extern.h>
@@ -58,9 +61,20 @@ __KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.24 2022/01/22 15:10:31 skrll Exp $");
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
+#if defined(PCI_NETBSD_ENABLE_IDE)
+#include <dev/pci/pciide_piix_reg.h>
+#endif /* PCI_NETBSD_ENABLE_IDE */
#include <dev/ic/i8259reg.h>
+#include "com.h"
+#if NCOM > 0
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+int comcnrate = 38400; /* XXX should be config option */
+#endif /* NCOM > 0 */
+
#define ICU_LEN 16 /* number of ISA IRQs */
@@ -169,6 +183,7 @@ static void
pcib_attach(device_t parent, device_t self, void *aux)
{
struct pci_attach_args * const pa = aux;
+ struct malta_config *mcp = &malta_configuration;
struct pcib_softc * const sc = device_private(self);
const char * const xname = device_xname(self);
char devinfo[256];
@@ -202,6 +217,51 @@ pcib_attach(device_t parent, device_t self, void *aux)
error);
sc->sc_dmat->_may_bounce = malta_isa_dma_may_bounce;
+ /*
+ * Calibrate the timer if YAMON failed to tell us.
+ */
+ if (!mcp->freqok) {
+ bus_space_handle_t sh;
+
+ bus_space_map(pa->pa_iot, MALTA_RTCADR, 2, 0, &sh);
+ malta_cal_timer(pa->pa_iot, sh);
+ bus_space_unmap(pa->pa_iot, sh, 2);
+ }
+
+#if defined(PCI_NETBSD_ENABLE_IDE)
+ /*
+ * Perhaps PMON has not enabled the IDE controller. Easy to
+ * fix -- just set the ENABLE bits for each channel in the
+ * IDETIM register. Just clear all the bits for the channel
+ * except for the ENABLE bits -- the `pciide' driver will
+ * properly configure it later.
+ */
+ pcireg_t idetim = 0;
+ if (PCI_NETBSD_ENABLE_IDE & 0x01)
+ idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
+ if (PCI_NETBSD_ENABLE_IDE & 0x02)
+ idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
+
+ /* pciide0 is pci device 10, function 1 */
+ pcitag_t idetag = pci_make_tag(pa->pa_pc, 0, 10, 1);
+ pci_conf_write(pa->pa_pc, idetag, PIIX_IDETIM, idetim);
+#endif
+
+#if 1
+ /*
+ * Delay to allow firmware putchars to complete.
+ * FIFO depth * character time.
+ * character time = (1000000 / (defaultrate / 10))
+ */
+ delay(160000000 / comcnrate);
+ if (comcnattach(sc->sc_iot, MALTA_UART0ADR, comcnrate,
+ COM_FREQ, COM_TYPE_NORMAL,
+ (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) != 0)
+ panic("malta: unable to initialize serial console");
+#else
+ panic("malta: not configured to use serial console");
+#endif /* NCOM > 0 */
+
/*
* Map the PIC/ELCR registers.
*/
diff --git a/sys/arch/mips/include/pci_machdep.h b/sys/arch/mips/include/pci_machdep.h
index 47b64e9b6ac3..ce971802b7c1 100644
--- a/sys/arch/mips/include/pci_machdep.h
+++ b/sys/arch/mips/include/pci_machdep.h
@@ -74,6 +74,9 @@ struct mips_pci_chipset {
int, int (*)(void *), void *);
void (*pc_intr_disestablish)(void *, void *);
+#ifdef __HAVE_PCI_CONF_HOOK
+ int (*pc_conf_hook)(void *, int, int, int, pcireg_t);
+#endif
void (*pc_conf_interrupt)(void *, int, int, int,
int, int *);
@@ -109,6 +112,10 @@ struct mips_pci_chipset {
(*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (h), (a))
#define pci_intr_disestablish(c, iv) \
(*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
+#ifdef __HAVE_PCI_CONF_HOOK
+#define pci_conf_hook(c, b, d, f, id) \
+ (*(c)->pc_conf_hook)((c)->pc_conf_v, (b), (d), (f), (id))
+#endif
#define pci_conf_interrupt(c, b, d, p, s, lp) \
(*(c)->pc_conf_interrupt)((c)->pc_intr_v, (b), (d), (p), (s), (lp))
--
(Contact us)
$NetBSD: query-full-pr,v 1.47 2022/09/11 19:34:41 kim Exp $
$NetBSD: gnats_config.sh,v 1.9 2014/08/02 14:16:04 spz Exp $
Copyright © 1994-2022
The NetBSD Foundation, Inc. ALL RIGHTS RESERVED.
Home