NetBSD Problem Report #57240
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for <gnats-bugs@gnats.NetBSD.org>; Mon, 20 Feb 2023 20:18:38 +0000 (UTC)
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Date: Mon, 20 Feb 2023 20:18:37 +0000 (UTC)
From: campbell+netbsd@mumble.net
Reply-To: campbell+netbsd@mumble.net
To: gnats-bugs@NetBSD.org
Subject: Missing store-before-store barriers in cpu_switchto on non-TSO MP platforms
X-Send-Pr-Version: www-1.0
>Number: 57240
>Category: kern
>Synopsis: Missing store-before-load barriers in cpu_switchto
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: kern-bug-people
>State: needs-pullups
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Mon Feb 20 20:20:00 +0000 2023
>Closed-Date:
>Last-Modified: Wed Aug 02 13:49:51 +0000 2023
>Originator: Taylor R Campbell
>Release: current
>Organization:
The NeFoundtBSatio Dn
>Environment:
slowly suffocating on carbon gases from humanity's intoxication with fossil fuel
>Description:
The mutex(9) implementation is designed to let mutex_exit run without atomic read/modify/write (CAS, LL/SC), as long as the sequence that tests for waiters and stores to release the lock can't be preempted.
This avoids a substantial cost in uncontended mutex_exit, but requires some care both in the sleeping path of mutex_enter (specifically, mutex_vector_enter) and in the cpu_switchto path which changes which thread is running on a CPU.
The sleeping path of mutex_vector_enter relies on being able to tell whether the owner of the CPU will definitely notice that there are waiters, in which case sleeping is safe; or whether the owner may be on the CPU, may have failed to notice the waiters, and may have clobbered the waiters bit in releasing the lock, in which case sleeping may deadlock and another iteration of spinning is necessary.
Specifically, mutex_vector_enter will set the waiters bit (with an atomic read/modify/write), and then try to discern which of the six cases around possible mutex_exit and thread-switch, or thread-switch and mutex_exit, the owner may be in:
1. (a) [cpu_switchto] ci->ci_curlwp = owner; (b) [mutex_exit] mtx->mtx_owner = 0
2. (a) [mutex_exit] mtx->mtx_owner = 0; (b) [cpu_switchto] ci->ci_curlwp = otherlwp
The six cases are before 1(a), between 1(a) and 1(b), or after 1(b); or before 2(a), between 2(a) and 2(b), or after 2(b).
mutex_vector_enter loads:
1. owner := load(&mtx->mtx_owner) & MUTEX_THREAD,
2. oncpu := load(&owner->l_cpu->ci_curlwp) == owner
3. haswaiters := load(&mtx->mtx_owner) & MUTEX_BIT_WAITERS
These loads are ordered with membar_consumer (load-before-load). The corresponding stores, in mutex_exit and cpu_switchto, must be ordered by membar_producer or equivalent (store-before-store).
On x86 and any architecture with TSO (like all sparc as far as I'm aware), no explicit barriers are needed because the loads and stores happen in order anyway and there is no store-before-load ordering, the only ordering which would require an explicit barrier.
On arm32 and aarch64, the barrier between 1(a) and 1(b) is currently in cpu_switchto; all other non-TSO MP architectures appear to be missing it.
On aarch64, it turns out that there is no need for an explicit barrier between 1(a) and 1(b), because the store to set mtx->mtx_owner = 0 only happens in one of three ways:
- with stlxr, which implies the necessary ordering anyway in a single nonpreemptible instruction that simultaneously serves as a barrier and a store;
- at splhigh (and therefore nonpreemptible) in MUTEX_RELEASE, which issues membar_release (enough for store-before-store) and then mtx->mtx_owner = 0; or
- under the mutex's turnstile lock (and therefore serialized with mutex_vector_enter) in MUTEX_RELEASE.
Finally, all non-TSO MP architectures (aarch64, alpha, arm32, ia64, mips, powerpc, riscv) appear to be missing the barrier between 2(a) and 2(b).
P.S. On all MP architectures except x86, the mutex_exit stub uses an atomic CAS or LL/SC anyway. (x86 uses CMPXCHG, but not LOCK CMPXCHG, so it can't be interrupted in the middle but isn't an atomic r/m/w as witnessed by other CPUs.) And normally, mutex_vector_exit only does MUTEX_RELEASE under the mutex's turnstile lock. So the only path that is actually affected by missing barriers is the path in mutex_vector_exit under #ifdef LOCKDEBUG which uses splhigh to avoid preemption, instead of taking the mutex's turnstile lock which would presumably sprout large volumes of useless lockdebug data. Perhaps we could get a performance win by teaching these architectures to use RAS instead of atomic CAS or LL/SC in their mutex_exit stubs. We could alternatively nix the splhigh/MUTEX_RELEASE path under #ifdef LOCKDEBUG in mutex_vector_exit, but that might severely damage the already-abysmal performance of LOCKDEBUG; we could alternatively put the barriers in cpu_switchto under #ifdef LOCK
DEBUG, but further deviation between LOCKDEBUG and !LOCKDEBUG kernels might damage the value of LOCKDEBUG as a diagnostic tool, and would prevent a potential RAS optimization in mutex_exit, which is generally a much hotter path than cpu_switchto.
>How-To-Repeat:
something about running /usr/games/worms for hours under LOCKDEBUG, according to mlelstv@, who I can only conclude must be very bored
>Fix:
Change each cpu_switchto routine so that when it sets the local struct cpu_info::ci_curlwp it issues store-before-store barriers on both sides:
1. membar_producer();
2. ci->ci_curlwp = newlwp;
3. membar_producer();
Add comments explaining what's up and cross-referencing kern_mutex.c in more than the cryptic level of detail they currently have.
Exceptions for optimization:
- When entering a softint for the first time, (3) may be unnecessary because no mutexes can be held by that softint lwp, and softint lwps can't (currently?) be preempted (at most, they can only voluntarily sleep on locks).
- On aarch64, no barrier may be needed at (3) because mutex_exit always issues a barrier and store nonpreemptibly, either with an STLXR instruction, at splhigh, or with the mutex's turnstile lock held.
Update the comments in kern_mutex.c should so that they are written in terms of program ordering semantics and matching load-before-load and store-before-store barriers, not in terms of obscure implementation details like acquiring and releasing cache lines, and should cross-reference cpu_switchto. Any exceptions should be documented both where the barrier would have gone, and where there's logic that renders that barrier unnecessary if appropriate.
Memorialize this scheme in the wiki or something and add links to it in the code.
>Release-Note:
>Audit-Trail:
From: Taylor R Campbell <riastradh@NetBSD.org>
To: gnats-bugs@NetBSD.org
Cc:
Subject: Re: kern/57240: Missing store-before-store barriers in cpu_switchto on non-TSO MP platforms
Date: Thu, 23 Feb 2023 10:54:08 +0000
Another potential optimization:
- If __HAVE_PREEMPTION is not defined, i.e., if there can be no kernel
preemption, the barrier in cpu_switchto at (3) after setting
ci->ci_curlwp can be omitted because any following mutex_exit always
issues a (stronger) barrier and store nonpreemptibly (since
everything in the kernel is nonpreemptible).
However, this might break in the face of softints, which as far as I'm
aware can preempt kernel threads even if non-softint threads can't
preempt other kernel threads (and softints can hold adaptive mutexes
so we can't just ignore them like we can ignore hard interrupts).
From: Taylor R Campbell <riastradh@NetBSD.org>
To: gnats-bugs@NetBSD.org
Cc:
Subject: Re: kern/57240: Missing store-before-store barriers in cpu_switchto on non-TSO MP platforms
Date: Thu, 23 Feb 2023 12:43:28 +0000
I sat down this morning to try to prove that either mutex_vector_enter
succeeds, or an eventual mutex_exit will wake it up. But I failed.
It looks like store-before-store barriers are not enough on their own,
and never have been, and both sides (mutex_vector_enter and
cpu_switchto) need the dreaded store-before-load barrier.
Let's recap the algorithm (with some irrelevant bits omitted -- spin
optimizations, KERNEL_LOCK coordination, and acquire/release membars).
mutex_vector_enter:
N1. load owner :=3D mtx->mtx_owner
N2. try CAS(&mtx->mtx_owner, 0, curlwp); on success, return
N3. lock turnstile
N4. try CAS(&mtx->mtx_owner, owner, owner|MUTEX_BIT_WAITERS);
on failure, unlock turnstile and restart
N5. if owner->l_cpu->ci_curlwp =3D=3D owner (owner on CPU), restart=20
N6. reload mtx->mtx_owner; if MUTEX_BIT_WAITERS clear, restart
N7. sleep (unlocks turnstile) and restart
mutex_exit, surrounded by cpu_switchto before (from otherlwp) and
after (back to otherlwp):
X1. [cpu_switchto] store curcpu()->ci_curlwp :=3D owner
...
X2. Without preemption:
(a) load owner :=3D mtx->mtx_owner
(b) if owner !=3D curlwp, go to X2
(c) store mtx->mtx_owner :=3D 0
(d) return
X3. lock turnstile
X4. wake waiters and unlock turnstile
...
X5. [cpu_switchto] store curcpu()->ci_curlwp :=3D otherlwp
Here's a possible sequence of events on two CPUs:
cpu1 (mutex_exit, lwp1) cpu2 (mutex_enter)
----------------------- ------------------
X1. store curcpu()->ci_curlwp :=3D lwp1
*** stuck in store buffer
X2(a). load mtx->mtx_owner
(reads out lwp1)
N4. CAS store mtx->mtx_owner
:=3D lwp1|MUTEX_BIT_WAITERS
X2(b). if owner !=3D curlwp go to X2
(branch not taken)
N5. load owner->l_cpu->ci_curlwp
*** reads out otherlwp!
X1'. store buffer finally flushes, too late
N6. reload mtx->mtx_owner
(MUTEX_BIT_WAITERS still set)
X2(c). store mtx->mtx_owner :=3D 0
X2(d). return
N7. sleep forever
It's not enough to issue a store-before-store barrier between X1
(curcpu()->ci_curlwp =3D owner in cpu_switchto) and X2 (mutex_exit) --
the stores are already ordered in this sequence of events.
Inserting store-before-load barriers between X1 and X2, and between N4
and N5, prevents this scenario: with these barriers, mutex_exit can't
examine mtx->mtx_owner until mutex_vector_enter would see that the
owner is running again, and mutex_vector_enter can't test whether the
owner is running again until mutex_exit would see MUTEX_BIT_WAITERS.
(The same issue applies to ci->ci_biglock_wanted for KERNEL_LOCK
coordination.)
I couldn't find any way to avoid the store-before-load barriers in my
proof sketches. When I realized this, I decided to check what Solaris
does, and sure enough, there's store-before-load on both sides, in
mutex_vector_enter and in `resume' (equivalent of cpu_switchto), and a
long comment in mutex.c explaining the reasoning I came upon:
https://github.com/illumos/illumos-gate/blob/9da20b8a0eca3f70a8e2ba38926902=
59d3ec6cb6/usr/src/uts/common/os/mutex.c
https://github.com/illumos/illumos-gate/blob/9da20b8a0eca3f70a8e2ba38926902=
59d3ec6cb6/usr/src/uts/common/os/mutex.c#L429-L431
https://github.com/illumos/illumos-gate/blob/f0089e391b2bc4be2755f1a1b51fb4=
cd9b8f3988/usr/src/uts/sun4/ml/swtch.s#L296-L297
https://github.com/illumos/illumos-gate/blob/f0089e391b2bc4be2755f1a1b51fb4=
cd9b8f3988/usr/src/uts/intel/ml/swtch.s#L467-L468
So unless ad@ knows some magic proof techniques that bypass the
barriers both I and the Solaris authors think are necessary, I think
we need to put a store-before-load barrier in every cpu_switchto.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/aarch64/aarch64
Date: Thu, 23 Feb 2023 14:54:57 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:54:57 UTC 2023
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S locore.S
Log Message:
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.90 -r1.91 src/sys/arch/aarch64/aarch64/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/alpha/include
Date: Thu, 23 Feb 2023 14:55:10 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:55:10 UTC 2023
Modified Files:
src/sys/arch/alpha/include: asm.h
Log Message:
alpha: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/alpha/include/asm.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/arm
Date: Thu, 23 Feb 2023 14:55:25 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:55:25 UTC 2023
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
src/sys/arch/arm/arm32: cpuswitch.S
Log Message:
arm32: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/arm/armv6_start.S
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/arm/arm32/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/hppa/include
Date: Thu, 23 Feb 2023 14:55:37 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:55:36 UTC 2023
Modified Files:
src/sys/arch/hppa/include: cpu.h
Log Message:
hppa: Add missing barriers in cpu_switchto.
PR kern/57240
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/hppa/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/ia64/ia64
Date: Thu, 23 Feb 2023 14:55:47 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:55:47 UTC 2023
Modified Files:
src/sys/arch/ia64/ia64: machdep.c vm_machdep.c
Log Message:
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/ia64/ia64/machdep.c
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/ia64/ia64/vm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch
Date: Thu, 23 Feb 2023 14:56:00 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:56:00 UTC 2023
Modified Files:
src/sys/arch/evbmips/ingenic: cpu_startup.S
src/sys/arch/mips/include: asm.h
src/sys/arch/mips/mips: locore.S locore_mips3.S
Log Message:
mips: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/cpu_startup.S
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.228 -r1.229 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.115 -r1.116 src/sys/arch/mips/mips/locore_mips3.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/powerpc/powerpc
Date: Thu, 23 Feb 2023 14:56:12 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:56:12 UTC 2023
Modified Files:
src/sys/arch/powerpc/powerpc: locore_subr.S
Log Message:
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/powerpc/powerpc/locore_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/riscv/riscv
Date: Thu, 23 Feb 2023 14:56:23 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:56:23 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
riscv: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/cpu_switch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/sparc/sparc
Date: Thu, 23 Feb 2023 14:56:38 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:56:37 UTC 2023
Modified Files:
src/sys/arch/sparc/sparc: locore.s
Log Message:
sparc: Add missing barriers in cpu_switchto.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.283 -r1.284 src/sys/arch/sparc/sparc/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/sparc64/sparc64
Date: Thu, 23 Feb 2023 14:56:56 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:56:56 UTC 2023
Modified Files:
src/sys/arch/sparc64/sparc64: locore.s
Log Message:
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.431 -r1.432 src/sys/arch/sparc64/sparc64/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/vax/vax
Date: Thu, 23 Feb 2023 14:57:09 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:57:09 UTC 2023
Modified Files:
src/sys/arch/vax/vax: subr.S
Log Message:
vax: Note where cpu_switchto needs barriers.
PR kern/57240
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
To generate a diff of this commit:
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/vax/vax/subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/kern
Date: Thu, 23 Feb 2023 14:57:29 +0000
Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:57:29 UTC 2023
Modified Files:
src/sys/kern: kern_lock.c kern_mutex.c
Log Message:
KERNEL_LOCK(9): Minor tweaks to ci->ci_biglock_wanted access.
1. Use atomic_load_relaxed to read ci->ci_biglock_wanted from another
CPU, for clarity and to avoid the appearance of data races in thread
sanitizers. (Reading ci->ci_biglock_wanted on the local CPU need
not be atomic because no other CPU can be writing to it.)
2. Use atomic_store_relaxed to update ci->ci_biglock_wanted when we
start to spin, to avoid the appearance of data races.
3. Add comments to explain what's going on and cross-reference the
specific matching membars in mutex_vector_enter.
related to PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.182 -r1.183 src/sys/kern/kern_lock.c
cvs rdiff -u -r1.102 -r1.103 src/sys/kern/kern_mutex.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/aarch64/aarch64
Date: Wed, 1 Mar 2023 08:17:24 +0000
Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:17:24 UTC 2023
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S
Log Message:
aarch64: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/aarch64/aarch64/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/arm/arm32
Date: Wed, 1 Mar 2023 08:17:53 +0000
Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:17:53 UTC 2023
Modified Files:
src/sys/arch/arm/arm32: cpuswitch.S
Log Message:
arm32: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/arm/arm32/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/mips/mips
Date: Wed, 1 Mar 2023 08:18:04 +0000
Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:18:04 UTC 2023
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
mips: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.229 -r1.230 src/sys/arch/mips/mips/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/powerpc/powerpc
Date: Wed, 1 Mar 2023 08:18:13 +0000
Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:18:13 UTC 2023
Modified Files:
src/sys/arch/powerpc/powerpc: locore_subr.S
Log Message:
powerpc: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.67 -r1.68 src/sys/arch/powerpc/powerpc/locore_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/riscv/riscv
Date: Wed, 1 Mar 2023 08:18:24 +0000
Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:18:24 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
riscv: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu_switch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch/sparc64/sparc64
Date: Wed, 1 Mar 2023 08:18:39 +0000
Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:18:39 UTC 2023
Modified Files:
src/sys/arch/sparc64/sparc64: locore.s
Log Message:
sparc64: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.432 -r1.433 src/sys/arch/sparc64/sparc64/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Taylor R Campbell" <riastradh@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: src/sys/arch
Date: Wed, 1 Mar 2023 08:38:51 +0000
Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:38:50 UTC 2023
Modified Files:
src/sys/arch/amd64/amd64: locore.S spl.S
src/sys/arch/i386/i386: locore.S spl.S
Log Message:
x86: Expand on comments on ordering around stores to ci_curlwp.
No functional change intended.
PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.216 -r1.217 src/sys/arch/amd64/amd64/locore.S
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/amd64/amd64/spl.S
cvs rdiff -u -r1.192 -r1.193 src/sys/arch/i386/i386/locore.S
cvs rdiff -u -r1.57 -r1.58 src/sys/arch/i386/i386/spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
State-Changed-From-To: open->needs-pullups
State-Changed-By: dholland@NetBSD.org
State-Changed-When: Fri, 12 May 2023 19:02:19 +0000
State-Changed-Why:
this doesn't seem to have broken HEAD so it's probably time to pull it up
State-Changed-From-To: needs-pullups->pending-pullups
State-Changed-By: riastradh@NetBSD.org
State-Changed-When: Sat, 29 Jul 2023 10:36:44 +0000
State-Changed-Why:
pullup-10 #264, pulllup-9 #1676, pullup-8 #1859
From: "Martin Husemann" <martin@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: [netbsd-10] src/sys/arch
Date: Mon, 31 Jul 2023 13:36:33 +0000
Module Name: src
Committed By: martin
Date: Mon Jul 31 13:36:32 UTC 2023
Modified Files:
src/sys/arch/aarch64/aarch64 [netbsd-10]: cpuswitch.S locore.S
src/sys/arch/alpha/include [netbsd-10]: asm.h
src/sys/arch/arm/arm [netbsd-10]: armv6_start.S
src/sys/arch/arm/arm32 [netbsd-10]: cpuswitch.S
src/sys/arch/evbmips/ingenic [netbsd-10]: cpu_startup.S
src/sys/arch/hppa/include [netbsd-10]: cpu.h
src/sys/arch/ia64/ia64 [netbsd-10]: machdep.c vm_machdep.c
src/sys/arch/mips/include [netbsd-10]: asm.h
src/sys/arch/mips/mips [netbsd-10]: locore.S locore_mips3.S
src/sys/arch/powerpc/powerpc [netbsd-10]: locore_subr.S
src/sys/arch/riscv/riscv [netbsd-10]: cpu_switch.S
src/sys/arch/sparc/sparc [netbsd-10]: locore.s
src/sys/arch/sparc64/sparc64 [netbsd-10]: locore.s
src/sys/arch/vax/vax [netbsd-10]: subr.S
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #264):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
riscv: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.39.4.1 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.89 -r1.89.2.1 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.44 -r1.44.20.1 src/sys/arch/alpha/include/asm.h
cvs rdiff -u -r1.37 -r1.37.4.1 src/sys/arch/arm/arm/armv6_start.S
cvs rdiff -u -r1.105 -r1.105.12.1 src/sys/arch/arm/arm32/cpuswitch.S
cvs rdiff -u -r1.1 -r1.1.52.1 src/sys/arch/evbmips/ingenic/cpu_startup.S
cvs rdiff -u -r1.12 -r1.12.4.1 src/sys/arch/hppa/include/cpu.h
cvs rdiff -u -r1.43 -r1.43.30.1 src/sys/arch/ia64/ia64/machdep.c
cvs rdiff -u -r1.17 -r1.17.4.1 src/sys/arch/ia64/ia64/vm_machdep.c
cvs rdiff -u -r1.71 -r1.71.4.1 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.228 -r1.228.12.1 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.115 -r1.115.20.1 src/sys/arch/mips/mips/locore_mips3.S
cvs rdiff -u -r1.66 -r1.66.4.1 src/sys/arch/powerpc/powerpc/locore_subr.S
cvs rdiff -u -r1.2 -r1.2.2.1 src/sys/arch/riscv/riscv/cpu_switch.S
cvs rdiff -u -r1.283 -r1.283.4.1 src/sys/arch/sparc/sparc/locore.s
cvs rdiff -u -r1.431 -r1.431.4.1 src/sys/arch/sparc64/sparc64/locore.s
cvs rdiff -u -r1.41 -r1.41.2.1 src/sys/arch/vax/vax/subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Martin Husemann" <martin@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: [netbsd-9] src/sys/arch
Date: Mon, 31 Jul 2023 13:44:17 +0000
Module Name: src
Committed By: martin
Date: Mon Jul 31 13:44:17 UTC 2023
Modified Files:
src/sys/arch/aarch64/aarch64 [netbsd-9]: cpuswitch.S locore.S
src/sys/arch/arm/arm [netbsd-9]: armv6_start.S
src/sys/arch/arm/arm32 [netbsd-9]: cpuswitch.S
src/sys/arch/evbmips/ingenic [netbsd-9]: cpu_startup.S
src/sys/arch/hppa/include [netbsd-9]: cpu.h
src/sys/arch/ia64/ia64 [netbsd-9]: machdep.c vm_machdep.c
src/sys/arch/mips/include [netbsd-9]: asm.h
src/sys/arch/mips/mips [netbsd-9]: locore.S locore_mips3.S
src/sys/arch/powerpc/powerpc [netbsd-9]: locore_subr.S
src/sys/arch/sparc/sparc [netbsd-9]: locore.s
src/sys/arch/sparc64/sparc64 [netbsd-9]: locore.s
src/sys/arch/vax/vax [netbsd-9]: subr.S
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1676):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
sys/arch/alpha/include/asm.h: revision 1.45
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
To generate a diff of this commit:
cvs rdiff -u -r1.11.4.1 -r1.11.4.2 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.39.2.5 -r1.39.2.6 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.14 -r1.14.2.1 src/sys/arch/arm/arm/armv6_start.S
cvs rdiff -u -r1.93 -r1.93.4.1 src/sys/arch/arm/arm32/cpuswitch.S
cvs rdiff -u -r1.1 -r1.1.26.1 src/sys/arch/evbmips/ingenic/cpu_startup.S
cvs rdiff -u -r1.5 -r1.5.4.1 src/sys/arch/hppa/include/cpu.h
cvs rdiff -u -r1.43 -r1.43.4.1 src/sys/arch/ia64/ia64/machdep.c
cvs rdiff -u -r1.16 -r1.16.4.1 src/sys/arch/ia64/ia64/vm_machdep.c
cvs rdiff -u -r1.55 -r1.55.4.1 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.219.4.1 -r1.219.4.2 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.114 -r1.114.8.1 src/sys/arch/mips/mips/locore_mips3.S
cvs rdiff -u -r1.57.4.2 -r1.57.4.3 src/sys/arch/powerpc/powerpc/locore_subr.S
cvs rdiff -u -r1.274 -r1.274.2.1 src/sys/arch/sparc/sparc/locore.s
cvs rdiff -u -r1.421 -r1.421.2.1 src/sys/arch/sparc64/sparc64/locore.s
cvs rdiff -u -r1.36 -r1.36.4.1 src/sys/arch/vax/vax/subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Martin Husemann" <martin@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: [netbsd-8] src/sys/arch
Date: Mon, 31 Jul 2023 13:56:16 +0000
Module Name: src
Committed By: martin
Date: Mon Jul 31 13:56:15 UTC 2023
Modified Files:
src/sys/arch/aarch64/aarch64 [netbsd-8]: locore.S
src/sys/arch/arm/arm32 [netbsd-8]: cpuswitch.S
src/sys/arch/evbmips/ingenic [netbsd-8]: cpu_startup.S
src/sys/arch/hppa/include [netbsd-8]: cpu.h
src/sys/arch/ia64/ia64 [netbsd-8]: machdep.c vm_machdep.c
src/sys/arch/mips/include [netbsd-8]: asm.h
src/sys/arch/mips/mips [netbsd-8]: locore.S locore_mips3.S
src/sys/arch/powerpc/powerpc [netbsd-8]: locore_subr.S
src/sys/arch/sparc/sparc [netbsd-8]: locore.s
src/sys/arch/sparc64/sparc64 [netbsd-8]: locore.s
src/sys/arch/vax/vax [netbsd-8]: subr.S
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1859):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
(applied also to sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/cortex_init.S)
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/alpha/include/asm.h: revision 1.45
(applied to sys/arch/alpha/alpha/multiproc.s)
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.1.22.1 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.90 -r1.90.10.1 src/sys/arch/arm/arm32/cpuswitch.S
cvs rdiff -u -r1.1 -r1.1.12.1 src/sys/arch/evbmips/ingenic/cpu_startup.S
cvs rdiff -u -r1.3 -r1.3.10.1 src/sys/arch/hppa/include/cpu.h
cvs rdiff -u -r1.38 -r1.38.6.1 src/sys/arch/ia64/ia64/machdep.c
cvs rdiff -u -r1.13 -r1.13.6.1 src/sys/arch/ia64/ia64/vm_machdep.c
cvs rdiff -u -r1.54 -r1.54.6.1 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.208 -r1.208.8.1 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.113 -r1.113.8.1 src/sys/arch/mips/mips/locore_mips3.S
cvs rdiff -u -r1.55 -r1.55.6.1 src/sys/arch/powerpc/powerpc/locore_subr.S
cvs rdiff -u -r1.268.30.1 -r1.268.30.2 src/sys/arch/sparc/sparc/locore.s
cvs rdiff -u -r1.411 -r1.411.2.1 src/sys/arch/sparc64/sparc64/locore.s
cvs rdiff -u -r1.34 -r1.34.2.1 src/sys/arch/vax/vax/subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Martin Husemann" <martin@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/57240 CVS commit: [netbsd-8] src/sys/arch
Date: Mon, 31 Jul 2023 14:26:26 +0000
Module Name: src
Committed By: martin
Date: Mon Jul 31 14:26:26 UTC 2023
Modified Files:
src/sys/arch/alpha/alpha [netbsd-8]: locore.s multiproc.s
src/sys/arch/arm/cortex [netbsd-8]: a9_mpsubr.S cortex_init.S
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1859):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
(applied also to sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/cortex_init.S)
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/alpha/include/asm.h: revision 1.45
(applied to sys/arch/alpha/alpha/multiproc.s)
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
To generate a diff of this commit:
cvs rdiff -u -r1.122 -r1.122.32.1 src/sys/arch/alpha/alpha/locore.s
cvs rdiff -u -r1.13 -r1.13.80.1 src/sys/arch/alpha/alpha/multiproc.s
cvs rdiff -u -r1.47.8.2 -r1.47.8.3 src/sys/arch/arm/cortex/a9_mpsubr.S
cvs rdiff -u -r1.1 -r1.1.12.1 src/sys/arch/arm/cortex/cortex_init.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
State-Changed-From-To: pending-pullups->needs-pullups
State-Changed-By: riastradh@NetBSD.org
State-Changed-When: Wed, 02 Aug 2023 13:49:51 +0000
State-Changed-Why:
fixed in HEAD and pulled up to 10, 9, 8
micro-optimization for softint case could still be pulled up to 10:wq
>Unformatted:
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$NetBSD: query-full-pr,v 1.47 2022/09/11 19:34:41 kim Exp $
$NetBSD: gnats_config.sh,v 1.9 2014/08/02 14:16:04 spz Exp $
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