NetBSD Problem Report #57943
From johann@sinyax.net Sat Feb 17 17:52:30 2024
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by mollari.NetBSD.org (Postfix) with ESMTPS id 410C11A9239
for <gnats-bugs@gnats.NetBSD.org>; Sat, 17 Feb 2024 17:52:30 +0000 (UTC)
Message-Id: <20240217174937.94CBC10A6F@beltix.localdomain>
Date: Sat, 17 Feb 2024 18:49:37 +0100 (CET)
From: johann@sinyax.net
Reply-To: johann@sinyax.net
To: gnats-bugs@NetBSD.org
Subject: [PATCH] rk3588: CRU improvements (resets and more clocks)
X-Send-Pr-Version: 3.95
>Number: 57943
>Category: port-evbarm
>Synopsis: rk3588: CRU improvements (resets and more clocks)
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: tnn
>State: open
>Class: change-request
>Submitter-Id: net
>Arrival-Date: Sat Feb 17 17:55:00 +0000 2024
>Last-Modified: Thu Apr 18 07:29:10 +0000 2024
>Originator: Johann Rudloff
>Release: NetBSD 10.99.10
>Organization:
>Environment:
System: NetBSD arm64 10.99.10 NetBSD 10.99.10 (ROCK5B) #321: Sat Feb 17 17:35:51 CET 2024 cypheon@beltix:/home/cypheon/obj-aarch64/sys/arch/evbarm/compile/ROCK5B evbarm
Architecture: aarch64
Machine: evbarm
>Description:
This patch groups together some improvements to CRU support on the RK3588 SoC,
most importantly it enables support for soft resets (SRSTs).
Included changes:
* introduce possibility to use a look-up-table from SRST ID -> register+bit
(earlier Rockchip SoCs encoded register+bit directly in the SRST ID, but
for RK3588, the ID is just an opaque identifier, so a mapping is required)
* add `#define`s for all RK3588 SRST constants
* add register+bit mappings for some (not all) RK3588 SRST IDs, will add more as
required for the next drivers
* add some additional RK3588 clock definitions that have been missing
Please let me know in case I should split it into smaller patches.
>How-To-Repeat:
This patch by itself can not be tested easily, but provides the foundation for further
rk3588 drivers I'm preparing to submit.
>Fix:
Patch download: https://sinyax.net/pub/netbsd/rk3588-cru.patch
sys/arch/arm/rockchip/rk3588_cru.c | 133 ++++++++
sys/arch/arm/rockchip/rk3588_cru.h | 661 +++++++++++++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk_cru.c | 17 +-
sys/arch/arm/rockchip/rk_cru.h | 3 +
4 files changed, 813 insertions(+), 1 deletion(-)
diff --git a/sys/arch/arm/rockchip/rk3588_cru.c b/sys/arch/arm/rockchip/rk3588_cru.c
index dc11ad04f004..2515e1727ca5 100644
--- a/sys/arch/arm/rockchip/rk3588_cru.c
+++ b/sys/arch/arm/rockchip/rk3588_cru.c
@@ -2882,6 +2882,47 @@ static struct rk_cru_clk rk3588_cru_clks[] = {
RK_GATE(RK3588_ACLK_AV1, "aclk_av1", "aclk_av1_pre",
CLKGATE_CON(0, 68), 2),
+ RK_GATE(RK3588_ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root",
+ CLKGATE_CON(0, 26), 6),
+ RK_GATE(RK3588_HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root",
+ CLKGATE_CON(0, 26), 8),
+ RK_GATE(RK3588_HCLK_NVM, "hclk_nvm", "hclk_nvm_root",
+ CLKGATE_CON(0, 31), 2),
+ RK_GATE(RK3588_ACLK_USB, "aclk_usb", "aclk_usb_root",
+ CLKGATE_CON(0, 42), 2),
+ RK_GATE(RK3588_HCLK_USB, "hclk_usb", "hclk_usb_root",
+ CLKGATE_CON(0, 42), 3),
+ RK_GATE(RK3588_ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root",
+ CLKGATE_CON(0, 44), 7),
+ RK_GATE(RK3588_ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root",
+ CLKGATE_CON(0, 44), 5),
+ RK_GATE(RK3588_ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root",
+ CLKGATE_CON(0, 48), 3),
+ RK_GATE(RK3588_HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root",
+ CLKGATE_CON(0, 48), 2),
+ RK_GATE(RK3588_HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root",
+ CLKGATE_CON(0, 40), 5),
+ RK_GATE(RK3588_ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root",
+ CLKGATE_CON(0, 40), 6),
+ RK_GATE(RK3588_HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root",
+ CLKGATE_CON(0, 41), 4),
+ RK_GATE(RK3588_ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root",
+ CLKGATE_CON(0, 41), 5),
+ RK_GATE(RK3588_ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root",
+ CLKGATE_CON(0, 55), 9),
+ RK_GATE(RK3588_HCLK_VO0, "hclk_vo0", "hclk_vo0_root",
+ CLKGATE_CON(0, 55), 5),
+ RK_GATE(RK3588_ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root",
+ CLKGATE_CON(0, 59), 6),
+ RK_GATE(RK3588_HCLK_VO1, "hclk_vo1", "hclk_vo1_root",
+ CLKGATE_CON(0, 59), 9),
+ RK_GATE(RK3588_ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root",
+ CLKGATE_CON(0, 68), 1),
+ RK_GATE(RK3588_PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root",
+ CLKGATE_CON(0, 68), 4),
+ RK_GATE(RK3588_HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root",
+ CLKGATE_CON(0, 75), 1),
+
#if 0
notyet
#define RK3588_SDIO_CON0 0x0c24
@@ -2896,6 +2937,96 @@ static struct rk_cru_clk rk3588_cru_clks[] = {
};
+#define RK3588_CRU_SOFTRST_CON(_con) (_con)
+#define RK3588_PMU1CRU_SOFTRST_CON(_con) (0x30000 / 4 + (_con))
+#define RK3588_SRST(_id, _reg, _bit) [_id] = (((_reg) * 16) | (_bit))
+
+static uint32_t rk3588_cru_softresets[] = {
+ RK3588_SRST(RK3588_SRST_A_TOP_BIU, RK3588_CRU_SOFTRST_CON(1), 3),
+ RK3588_SRST(RK3588_SRST_P_TOP_BIU, RK3588_CRU_SOFTRST_CON(1), 4),
+ RK3588_SRST(RK3588_SRST_P_CSIPHY0, RK3588_CRU_SOFTRST_CON(1), 6),
+ RK3588_SRST(RK3588_SRST_P_CSIPHY1, RK3588_CRU_SOFTRST_CON(1), 8),
+ RK3588_SRST(RK3588_SRST_A_TOP_M500_BIU, RK3588_CRU_SOFTRST_CON(1), 15),
+
+ RK3588_SRST(RK3588_SRST_A_TOP_M400_BIU, RK3588_CRU_SOFTRST_CON(2), 0),
+ RK3588_SRST(RK3588_SRST_A_TOP_S200_BIU, RK3588_CRU_SOFTRST_CON(2), 1),
+ RK3588_SRST(RK3588_SRST_A_TOP_S400_BIU, RK3588_CRU_SOFTRST_CON(2), 2),
+ RK3588_SRST(RK3588_SRST_A_TOP_M300_BIU, RK3588_CRU_SOFTRST_CON(2), 3),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0_INIT, RK3588_CRU_SOFTRST_CON(2), 8),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0_CMN, RK3588_CRU_SOFTRST_CON(2), 9),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0_LANE, RK3588_CRU_SOFTRST_CON(2), 10),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0_PCS, RK3588_CRU_SOFTRST_CON(2), 11),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1_INIT, RK3588_CRU_SOFTRST_CON(2), 15),
+
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1_CMN, RK3588_CRU_SOFTRST_CON(3), 0),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1_LANE, RK3588_CRU_SOFTRST_CON(3), 1),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1_PCS, RK3588_CRU_SOFTRST_CON(3), 2),
+ RK3588_SRST(RK3588_SRST_P_MIPI_DCPHY0, RK3588_CRU_SOFTRST_CON(3), 14),
+ RK3588_SRST(RK3588_SRST_P_MIPI_DCPHY0_GRF, RK3588_CRU_SOFTRST_CON(3), 15),
+
+ // TODO: CON04 - CON30
+
+ RK3588_SRST(RK3588_SRST_H_NVM_BIU, RK3588_CRU_SOFTRST_CON(31), 2),
+ RK3588_SRST(RK3588_SRST_A_NVM_BIU, RK3588_CRU_SOFTRST_CON(31), 3),
+ RK3588_SRST(RK3588_SRST_H_EMMC, RK3588_CRU_SOFTRST_CON(31), 4),
+ RK3588_SRST(RK3588_SRST_A_EMMC, RK3588_CRU_SOFTRST_CON(31), 5),
+ RK3588_SRST(RK3588_SRST_C_EMMC, RK3588_CRU_SOFTRST_CON(31), 6),
+ RK3588_SRST(RK3588_SRST_B_EMMC, RK3588_CRU_SOFTRST_CON(31), 7),
+ RK3588_SRST(RK3588_SRST_T_EMMC, RK3588_CRU_SOFTRST_CON(31), 8),
+ RK3588_SRST(RK3588_SRST_S_SFC, RK3588_CRU_SOFTRST_CON(31), 9),
+ RK3588_SRST(RK3588_SRST_H_SFC, RK3588_CRU_SOFTRST_CON(31), 10),
+ RK3588_SRST(RK3588_SRST_H_SFC_XIP, RK3588_CRU_SOFTRST_CON(31), 11),
+
+ // TODO: CON32 - CON71
+
+ RK3588_SRST(RK3588_SRST_P_USBDPGRF0, RK3588_CRU_SOFTRST_CON(72), 1),
+ RK3588_SRST(RK3588_SRST_P_USBDPPHY0, RK3588_CRU_SOFTRST_CON(72), 2),
+ RK3588_SRST(RK3588_SRST_P_USBDPGRF1, RK3588_CRU_SOFTRST_CON(72), 3),
+ RK3588_SRST(RK3588_SRST_P_USBDPPHY1, RK3588_CRU_SOFTRST_CON(72), 4),
+ RK3588_SRST(RK3588_SRST_P_HDPTX0, RK3588_CRU_SOFTRST_CON(72), 5),
+ RK3588_SRST(RK3588_SRST_P_HDPTX1, RK3588_CRU_SOFTRST_CON(72), 6),
+ RK3588_SRST(RK3588_SRST_P_APB2ASB_SLV_BOT_RIGHT, RK3588_CRU_SOFTRST_CON(72), 7),
+ RK3588_SRST(RK3588_SRST_P_USB2PHY_U3_0_GRF0, RK3588_CRU_SOFTRST_CON(72), 8),
+ RK3588_SRST(RK3588_SRST_P_USB2PHY_U3_1_GRF0, RK3588_CRU_SOFTRST_CON(72), 9),
+ RK3588_SRST(RK3588_SRST_P_USB2PHY_U2_0_GRF0, RK3588_CRU_SOFTRST_CON(72), 10),
+ RK3588_SRST(RK3588_SRST_P_USB2PHY_U2_1_GRF0, RK3588_CRU_SOFTRST_CON(72), 11),
+ RK3588_SRST(RK3588_SRST_HDPTX0_ROPLL, RK3588_CRU_SOFTRST_CON(72), 12),
+ RK3588_SRST(RK3588_SRST_HDPTX0_LCPLL, RK3588_CRU_SOFTRST_CON(72), 13),
+ RK3588_SRST(RK3588_SRST_HDPTX0, RK3588_CRU_SOFTRST_CON(72), 14),
+ RK3588_SRST(RK3588_SRST_HDPTX1_ROPLL, RK3588_CRU_SOFTRST_CON(72), 15),
+
+ RK3588_SRST(RK3588_SRST_HDPTX1_LCPLL, RK3588_CRU_SOFTRST_CON(73), 0),
+ RK3588_SRST(RK3588_SRST_HDPTX1, RK3588_CRU_SOFTRST_CON(73), 1),
+ RK3588_SRST(RK3588_SRST_HDPTX0_HDMIRXPHY_SET, RK3588_CRU_SOFTRST_CON(73), 2),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0, RK3588_CRU_SOFTRST_CON(73), 3),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0_LCPLL, RK3588_CRU_SOFTRST_CON(73), 4),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0_ROPLL, RK3588_CRU_SOFTRST_CON(73), 5),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY0_PCS_HS, RK3588_CRU_SOFTRST_CON(73), 6),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1, RK3588_CRU_SOFTRST_CON(73), 7),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1_LCPLL, RK3588_CRU_SOFTRST_CON(73), 8),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1_ROPLL, RK3588_CRU_SOFTRST_CON(73), 9),
+ RK3588_SRST(RK3588_SRST_USBDP_COMBO_PHY1_PCS_HS, RK3588_CRU_SOFTRST_CON(73), 10),
+ RK3588_SRST(RK3588_SRST_HDMIHDP0, RK3588_CRU_SOFTRST_CON(73), 12),
+ RK3588_SRST(RK3588_SRST_HDMIHDP1, RK3588_CRU_SOFTRST_CON(73), 13),
+
+ RK3588_SRST(RK3588_SRST_H_VAD, RK3588_PMU1CRU_SOFTRST_CON(3), 0),
+ RK3588_SRST(RK3588_SRST_HDPTX0_INIT, RK3588_PMU1CRU_SOFTRST_CON(3), 11),
+ RK3588_SRST(RK3588_SRST_HDPTX0_CMN, RK3588_PMU1CRU_SOFTRST_CON(3), 12),
+ RK3588_SRST(RK3588_SRST_HDPTX0_LANE, RK3588_PMU1CRU_SOFTRST_CON(3), 13),
+ RK3588_SRST(RK3588_SRST_HDPTX1_INIT, RK3588_PMU1CRU_SOFTRST_CON(3), 15),
+
+ RK3588_SRST(RK3588_SRST_HDPTX1_CMN, RK3588_PMU1CRU_SOFTRST_CON(4), 0),
+ RK3588_SRST(RK3588_SRST_HDPTX1_LANE, RK3588_PMU1CRU_SOFTRST_CON(4), 1),
+ RK3588_SRST(RK3588_SRST_M_MIPI_DCPHY0, RK3588_PMU1CRU_SOFTRST_CON(4), 3),
+ RK3588_SRST(RK3588_SRST_S_MIPI_DCPHY0, RK3588_PMU1CRU_SOFTRST_CON(4), 4),
+ RK3588_SRST(RK3588_SRST_M_MIPI_DCPHY0, RK3588_PMU1CRU_SOFTRST_CON(4), 5),
+ RK3588_SRST(RK3588_SRST_S_MIPI_DCPHY0, RK3588_PMU1CRU_SOFTRST_CON(4), 6),
+ RK3588_SRST(RK3588_SRST_OTGPHY_U3_0, RK3588_PMU1CRU_SOFTRST_CON(4), 7),
+ RK3588_SRST(RK3588_SRST_OTGPHY_U3_1, RK3588_PMU1CRU_SOFTRST_CON(4), 8),
+ RK3588_SRST(RK3588_SRST_OTGPHY_U2_0, RK3588_PMU1CRU_SOFTRST_CON(4), 9),
+ RK3588_SRST(RK3588_SRST_OTGPHY_U2_1, RK3588_PMU1CRU_SOFTRST_CON(4), 10),
+};
+
static void
rk3588_cru_init(struct rk_cru_softc *sc)
{
@@ -2919,6 +3050,8 @@ rk3588_cru_attach(device_t parent, device_t self, void *aux)
sc->sc_bst = faa->faa_bst;
sc->sc_clks = rk3588_cru_clks;
sc->sc_nclks = __arraycount(rk3588_cru_clks);
+ sc->sc_srst_lut = rk3588_cru_softresets;
+ sc->sc_nsrst = __arraycount(rk3588_cru_softresets);
sc->sc_grf_soc_status = 0x0480; /* XXX */
sc->sc_softrst_base = SOFTRST_CON(0, 0); /* XXX */
diff --git a/sys/arch/arm/rockchip/rk3588_cru.h b/sys/arch/arm/rockchip/rk3588_cru.h
index 7c63b1afdcbd..5c887104de8c 100644
--- a/sys/arch/arm/rockchip/rk3588_cru.h
+++ b/sys/arch/arm/rockchip/rk3588_cru.h
@@ -750,4 +750,665 @@
#define RK3588_PCLK_AV1_PRE 719
#define RK3588_HCLK_SDIO_PRE 720
+#define RK3588_SRST_A_TOP_BIU 0
+#define RK3588_SRST_P_TOP_BIU 1
+#define RK3588_SRST_P_CSIPHY0 2
+#define RK3588_SRST_CSIPHY0 3
+#define RK3588_SRST_P_CSIPHY1 4
+#define RK3588_SRST_CSIPHY1 5
+#define RK3588_SRST_A_TOP_M500_BIU 6
+#define RK3588_SRST_A_TOP_M400_BIU 7
+#define RK3588_SRST_A_TOP_S200_BIU 8
+#define RK3588_SRST_A_TOP_S400_BIU 9
+#define RK3588_SRST_A_TOP_M300_BIU 10
+#define RK3588_SRST_USBDP_COMBO_PHY0_INIT 11
+#define RK3588_SRST_USBDP_COMBO_PHY0_CMN 12
+#define RK3588_SRST_USBDP_COMBO_PHY0_LANE 13
+#define RK3588_SRST_USBDP_COMBO_PHY0_PCS 14
+#define RK3588_SRST_USBDP_COMBO_PHY1_INIT 15
+#define RK3588_SRST_USBDP_COMBO_PHY1_CMN 16
+#define RK3588_SRST_USBDP_COMBO_PHY1_LANE 17
+#define RK3588_SRST_USBDP_COMBO_PHY1_PCS 18
+#define RK3588_SRST_DCPHY0 19
+#define RK3588_SRST_P_MIPI_DCPHY0 20
+#define RK3588_SRST_P_MIPI_DCPHY0_GRF 21
+#define RK3588_SRST_DCPHY1 22
+#define RK3588_SRST_P_MIPI_DCPHY1 23
+#define RK3588_SRST_P_MIPI_DCPHY1_GRF 24
+#define RK3588_SRST_P_APB2ASB_SLV_CDPHY 25
+#define RK3588_SRST_P_APB2ASB_SLV_CSIPHY 26
+#define RK3588_SRST_P_APB2ASB_SLV_VCCIO3_5 27
+#define RK3588_SRST_P_APB2ASB_SLV_VCCIO6 28
+#define RK3588_SRST_P_APB2ASB_SLV_EMMCIO 29
+#define RK3588_SRST_P_APB2ASB_SLV_IOC_TOP 30
+#define RK3588_SRST_P_APB2ASB_SLV_IOC_RIGHT 31
+#define RK3588_SRST_P_CRU 32
+#define RK3588_SRST_A_CHANNEL_SECURE2VO1USB 33
+#define RK3588_SRST_A_CHANNEL_SECURE2CENTER 34
+#define RK3588_SRST_H_CHANNEL_SECURE2VO1USB 35
+#define RK3588_SRST_H_CHANNEL_SECURE2CENTER 36
+#define RK3588_SRST_P_CHANNEL_SECURE2VO1USB 37
+#define RK3588_SRST_P_CHANNEL_SECURE2CENTER 38
+#define RK3588_SRST_H_AUDIO_BIU 39
+#define RK3588_SRST_P_AUDIO_BIU 40
+#define RK3588_SRST_H_I2S0_8CH 41
+#define RK3588_SRST_M_I2S0_8CH_TX 42
+#define RK3588_SRST_M_I2S0_8CH_RX 43
+#define RK3588_SRST_P_ACDCDIG 44
+#define RK3588_SRST_H_I2S2_2CH 45
+#define RK3588_SRST_H_I2S3_2CH 46
+#define RK3588_SRST_M_I2S2_2CH 47
+#define RK3588_SRST_M_I2S3_2CH 48
+#define RK3588_SRST_DAC_ACDCDIG 49
+#define RK3588_SRST_H_SPDIF0 50
+#define RK3588_SRST_M_SPDIF0 51
+#define RK3588_SRST_H_SPDIF1 52
+#define RK3588_SRST_M_SPDIF1 53
+#define RK3588_SRST_H_PDM1 54
+#define RK3588_SRST_PDM1 55
+#define RK3588_SRST_A_BUS_BIU 56
+#define RK3588_SRST_P_BUS_BIU 57
+#define RK3588_SRST_A_GIC 58
+#define RK3588_SRST_A_GIC_DBG 59
+#define RK3588_SRST_A_DMAC0 60
+#define RK3588_SRST_A_DMAC1 61
+#define RK3588_SRST_A_DMAC2 62
+#define RK3588_SRST_P_I2C1 63
+#define RK3588_SRST_P_I2C2 64
+#define RK3588_SRST_P_I2C3 65
+#define RK3588_SRST_P_I2C4 66
+#define RK3588_SRST_P_I2C5 67
+#define RK3588_SRST_P_I2C6 68
+#define RK3588_SRST_P_I2C7 69
+#define RK3588_SRST_P_I2C8 70
+#define RK3588_SRST_I2C1 71
+#define RK3588_SRST_I2C2 72
+#define RK3588_SRST_I2C3 73
+#define RK3588_SRST_I2C4 74
+#define RK3588_SRST_I2C5 75
+#define RK3588_SRST_I2C6 76
+#define RK3588_SRST_I2C7 77
+#define RK3588_SRST_I2C8 78
+#define RK3588_SRST_P_CAN0 79
+#define RK3588_SRST_CAN0 80
+#define RK3588_SRST_P_CAN1 81
+#define RK3588_SRST_CAN1 82
+#define RK3588_SRST_P_CAN2 83
+#define RK3588_SRST_CAN2 84
+#define RK3588_SRST_P_SARADC 85
+#define RK3588_SRST_P_TSADC 86
+#define RK3588_SRST_TSADC 87
+#define RK3588_SRST_P_UART1 88
+#define RK3588_SRST_P_UART2 89
+#define RK3588_SRST_P_UART3 90
+#define RK3588_SRST_P_UART4 91
+#define RK3588_SRST_P_UART5 92
+#define RK3588_SRST_P_UART6 93
+#define RK3588_SRST_P_UART7 94
+#define RK3588_SRST_P_UART8 95
+#define RK3588_SRST_P_UART9 96
+#define RK3588_SRST_S_UART1 97
+#define RK3588_SRST_S_UART2 98
+#define RK3588_SRST_S_UART3 99
+#define RK3588_SRST_S_UART4 100
+#define RK3588_SRST_S_UART5 101
+#define RK3588_SRST_S_UART6 102
+#define RK3588_SRST_S_UART7 103
+#define RK3588_SRST_S_UART8 104
+#define RK3588_SRST_S_UART9 105
+#define RK3588_SRST_P_SPI0 106
+#define RK3588_SRST_P_SPI1 107
+#define RK3588_SRST_P_SPI2 108
+#define RK3588_SRST_P_SPI3 109
+#define RK3588_SRST_P_SPI4 110
+#define RK3588_SRST_SPI0 111
+#define RK3588_SRST_SPI1 112
+#define RK3588_SRST_SPI2 113
+#define RK3588_SRST_SPI3 114
+#define RK3588_SRST_SPI4 115
+#define RK3588_SRST_P_WDT0 116
+#define RK3588_SRST_T_WDT0 117
+#define RK3588_SRST_P_SYS_GRF 118
+#define RK3588_SRST_P_PWM1 119
+#define RK3588_SRST_PWM1 120
+#define RK3588_SRST_P_PWM2 121
+#define RK3588_SRST_PWM2 122
+#define RK3588_SRST_P_PWM3 123
+#define RK3588_SRST_PWM3 124
+#define RK3588_SRST_P_BUSTIMER0 125
+#define RK3588_SRST_P_BUSTIMER1 126
+#define RK3588_SRST_BUSTIMER0 127
+#define RK3588_SRST_BUSTIMER1 128
+#define RK3588_SRST_BUSTIMER2 129
+#define RK3588_SRST_BUSTIMER3 130
+#define RK3588_SRST_BUSTIMER4 131
+#define RK3588_SRST_BUSTIMER5 132
+#define RK3588_SRST_BUSTIMER6 133
+#define RK3588_SRST_BUSTIMER7 134
+#define RK3588_SRST_BUSTIMER8 135
+#define RK3588_SRST_BUSTIMER9 136
+#define RK3588_SRST_BUSTIMER10 137
+#define RK3588_SRST_BUSTIMER11 138
+#define RK3588_SRST_P_MAILBOX0 139
+#define RK3588_SRST_P_MAILBOX1 140
+#define RK3588_SRST_P_MAILBOX2 141
+#define RK3588_SRST_P_GPIO1 142
+#define RK3588_SRST_GPIO1 143
+#define RK3588_SRST_P_GPIO2 144
+#define RK3588_SRST_GPIO2 145
+#define RK3588_SRST_P_GPIO3 146
+#define RK3588_SRST_GPIO3 147
+#define RK3588_SRST_P_GPIO4 148
+#define RK3588_SRST_GPIO4 149
+#define RK3588_SRST_A_DECOM 150
+#define RK3588_SRST_P_DECOM 151
+#define RK3588_SRST_D_DECOM 152
+#define RK3588_SRST_P_TOP 153
+#define RK3588_SRST_A_GICADB_GIC2CORE_BUS 154
+#define RK3588_SRST_P_DFT2APB 155
+#define RK3588_SRST_P_APB2ASB_MST_TOP 156
+#define RK3588_SRST_P_APB2ASB_MST_CDPHY 157
+#define RK3588_SRST_P_APB2ASB_MST_BOT_RIGHT 158
+#define RK3588_SRST_P_APB2ASB_MST_IOC_TOP 159
+#define RK3588_SRST_P_APB2ASB_MST_IOC_RIGHT 160
+#define RK3588_SRST_P_APB2ASB_MST_CSIPHY 161
+#define RK3588_SRST_P_APB2ASB_MST_VCCIO3_5 162
+#define RK3588_SRST_P_APB2ASB_MST_VCCIO6 163
+#define RK3588_SRST_P_APB2ASB_MST_EMMCIO 164
+#define RK3588_SRST_A_SPINLOCK 165
+#define RK3588_SRST_P_OTPC_NS 166
+#define RK3588_SRST_OTPC_NS 167
+#define RK3588_SRST_OTPC_ARB 168
+#define RK3588_SRST_P_BUSIOC 169
+#define RK3588_SRST_P_PMUCM0_INTMUX 170
+#define RK3588_SRST_P_DDRCM0_INTMUX 171
+#define RK3588_SRST_P_DDR_DFICTL_CH0 172
+#define RK3588_SRST_P_DDR_MON_CH0 173
+#define RK3588_SRST_P_DDR_STANDBY_CH0 174
+#define RK3588_SRST_P_DDR_UPCTL_CH0 175
+#define RK3588_SRST_TM_DDR_MON_CH0 176
+#define RK3588_SRST_P_DDR_GRF_CH01 177
+#define RK3588_SRST_DFI_CH0 178
+#define RK3588_SRST_SBR_CH0 179
+#define RK3588_SRST_DDR_UPCTL_CH0 180
+#define RK3588_SRST_DDR_DFICTL_CH0 181
+#define RK3588_SRST_DDR_MON_CH0 182
+#define RK3588_SRST_DDR_STANDBY_CH0 183
+#define RK3588_SRST_A_DDR_UPCTL_CH0 184
+#define RK3588_SRST_P_DDR_DFICTL_CH1 185
+#define RK3588_SRST_P_DDR_MON_CH1 186
+#define RK3588_SRST_P_DDR_STANDBY_CH1 187
+#define RK3588_SRST_P_DDR_UPCTL_CH1 188
+#define RK3588_SRST_TM_DDR_MON_CH1 189
+#define RK3588_SRST_DFI_CH1 190
+#define RK3588_SRST_SBR_CH1 191
+#define RK3588_SRST_DDR_UPCTL_CH1 192
+#define RK3588_SRST_DDR_DFICTL_CH1 193
+#define RK3588_SRST_DDR_MON_CH1 194
+#define RK3588_SRST_DDR_STANDBY_CH1 195
+#define RK3588_SRST_A_DDR_UPCTL_CH1 196
+#define RK3588_SRST_A_DDR01_MSCH0 197
+#define RK3588_SRST_A_DDR01_RS_MSCH0 198
+#define RK3588_SRST_A_DDR01_FRS_MSCH0 199
+#define RK3588_SRST_A_DDR01_SCRAMBLE0 200
+#define RK3588_SRST_A_DDR01_FRS_SCRAMBLE0 201
+#define RK3588_SRST_A_DDR01_MSCH1 202
+#define RK3588_SRST_A_DDR01_RS_MSCH1 203
+#define RK3588_SRST_A_DDR01_FRS_MSCH1 204
+#define RK3588_SRST_A_DDR01_SCRAMBLE1 205
+#define RK3588_SRST_A_DDR01_FRS_SCRAMBLE1 206
+#define RK3588_SRST_P_DDR01_MSCH0 207
+#define RK3588_SRST_P_DDR01_MSCH1 208
+#define RK3588_SRST_P_DDR_DFICTL_CH2 209
+#define RK3588_SRST_P_DDR_MON_CH2 210
+#define RK3588_SRST_P_DDR_STANDBY_CH2 211
+#define RK3588_SRST_P_DDR_UPCTL_CH2 212
+#define RK3588_SRST_TM_DDR_MON_CH2 213
+#define RK3588_SRST_P_DDR_GRF_CH23 214
+#define RK3588_SRST_DFI_CH2 215
+#define RK3588_SRST_SBR_CH2 216
+#define RK3588_SRST_DDR_UPCTL_CH2 217
+#define RK3588_SRST_DDR_DFICTL_CH2 218
+#define RK3588_SRST_DDR_MON_CH2 219
+#define RK3588_SRST_DDR_STANDBY_CH2 220
+#define RK3588_SRST_A_DDR_UPCTL_CH2 221
+#define RK3588_SRST_P_DDR_DFICTL_CH3 222
+#define RK3588_SRST_P_DDR_MON_CH3 223
+#define RK3588_SRST_P_DDR_STANDBY_CH3 224
+#define RK3588_SRST_P_DDR_UPCTL_CH3 225
+#define RK3588_SRST_TM_DDR_MON_CH3 226
+#define RK3588_SRST_DFI_CH3 227
+#define RK3588_SRST_SBR_CH3 228
+#define RK3588_SRST_DDR_UPCTL_CH3 229
+#define RK3588_SRST_DDR_DFICTL_CH3 230
+#define RK3588_SRST_DDR_MON_CH3 231
+#define RK3588_SRST_DDR_STANDBY_CH3 232
+#define RK3588_SRST_A_DDR_UPCTL_CH3 233
+#define RK3588_SRST_A_DDR23_MSCH2 234
+#define RK3588_SRST_A_DDR23_RS_MSCH2 235
+#define RK3588_SRST_A_DDR23_FRS_MSCH2 236
+#define RK3588_SRST_A_DDR23_SCRAMBLE2 237
+#define RK3588_SRST_A_DDR23_FRS_SCRAMBLE2 238
+#define RK3588_SRST_A_DDR23_MSCH3 239
+#define RK3588_SRST_A_DDR23_RS_MSCH3 240
+#define RK3588_SRST_A_DDR23_FRS_MSCH3 241
+#define RK3588_SRST_A_DDR23_SCRAMBLE3 242
+#define RK3588_SRST_A_DDR23_FRS_SCRAMBLE3 243
+#define RK3588_SRST_P_DDR23_MSCH2 244
+#define RK3588_SRST_P_DDR23_MSCH3 245
+#define RK3588_SRST_ISP1 246
+#define RK3588_SRST_ISP1_VICAP 247
+#define RK3588_SRST_A_ISP1_BIU 248
+#define RK3588_SRST_H_ISP1_BIU 249
+#define RK3588_SRST_A_RKNN1 250
+#define RK3588_SRST_A_RKNN1_BIU 251
+#define RK3588_SRST_H_RKNN1 252
+#define RK3588_SRST_H_RKNN1_BIU 253
+#define RK3588_SRST_A_RKNN2 254
+#define RK3588_SRST_A_RKNN2_BIU 255
+#define RK3588_SRST_H_RKNN2 256
+#define RK3588_SRST_H_RKNN2_BIU 257
+#define RK3588_SRST_A_RKNN_DSU0 258
+#define RK3588_SRST_P_NPUTOP_BIU 259
+#define RK3588_SRST_P_NPU_TIMER 260
+#define RK3588_SRST_NPUTIMER0 261
+#define RK3588_SRST_NPUTIMER1 262
+#define RK3588_SRST_P_NPU_WDT 263
+#define RK3588_SRST_T_NPU_WDT 264
+#define RK3588_SRST_P_NPU_PVTM 265
+#define RK3588_SRST_P_NPU_GRF 266
+#define RK3588_SRST_NPU_PVTM 267
+#define RK3588_SRST_NPU_PVTPLL 268
+#define RK3588_SRST_H_NPU_CM0_BIU 269
+#define RK3588_SRST_F_NPU_CM0_CORE 270
+#define RK3588_SRST_T_NPU_CM0_JTAG 271
+#define RK3588_SRST_A_RKNN0 272
+#define RK3588_SRST_A_RKNN0_BIU 273
+#define RK3588_SRST_H_RKNN0 274
+#define RK3588_SRST_H_RKNN0_BIU 275
+#define RK3588_SRST_H_NVM_BIU 276
+#define RK3588_SRST_A_NVM_BIU 277
+#define RK3588_SRST_H_EMMC 278
+#define RK3588_SRST_A_EMMC 279
+#define RK3588_SRST_C_EMMC 280
+#define RK3588_SRST_B_EMMC 281
+#define RK3588_SRST_T_EMMC 282
+#define RK3588_SRST_S_SFC 283
+#define RK3588_SRST_H_SFC 284
+#define RK3588_SRST_H_SFC_XIP 285
+#define RK3588_SRST_P_GRF 286
+#define RK3588_SRST_P_DEC_BIU 287
+#define RK3588_SRST_P_PHP_BIU 288
+#define RK3588_SRST_A_PCIE_GRIDGE 289
+#define RK3588_SRST_A_PHP_BIU 290
+#define RK3588_SRST_A_GMAC0 291
+#define RK3588_SRST_A_GMAC1 292
+#define RK3588_SRST_A_PCIE_BIU 293
+#define RK3588_SRST_PCIE0_POWER_UP 294
+#define RK3588_SRST_PCIE1_POWER_UP 295
+#define RK3588_SRST_PCIE2_POWER_UP 296
+#define RK3588_SRST_PCIE3_POWER_UP 297
+#define RK3588_SRST_PCIE4_POWER_UP 298
+#define RK3588_SRST_P_PCIE0 299
+#define RK3588_SRST_P_PCIE1 300
+#define RK3588_SRST_P_PCIE2 301
+#define RK3588_SRST_P_PCIE3 302
+#define RK3588_SRST_P_PCIE4 303
+#define RK3588_SRST_A_PHP_GIC_ITS 304
+#define RK3588_SRST_A_MMU_PCIE 305
+#define RK3588_SRST_A_MMU_PHP 306
+#define RK3588_SRST_A_MMU_BIU 307
+#define RK3588_SRST_A_USB3OTG2 308
+#define RK3588_SRST_PMALIVE0 309
+#define RK3588_SRST_PMALIVE1 310
+#define RK3588_SRST_PMALIVE2 311
+#define RK3588_SRST_A_SATA0 312
+#define RK3588_SRST_A_SATA1 313
+#define RK3588_SRST_A_SATA2 314
+#define RK3588_SRST_RXOOB0 315
+#define RK3588_SRST_RXOOB1 316
+#define RK3588_SRST_RXOOB2 317
+#define RK3588_SRST_ASIC0 318
+#define RK3588_SRST_ASIC1 319
+#define RK3588_SRST_ASIC2 320
+#define RK3588_SRST_A_RKVDEC_CCU 321
+#define RK3588_SRST_H_RKVDEC0 322
+#define RK3588_SRST_A_RKVDEC0 323
+#define RK3588_SRST_H_RKVDEC0_BIU 324
+#define RK3588_SRST_A_RKVDEC0_BIU 325
+#define RK3588_SRST_RKVDEC0_CA 326
+#define RK3588_SRST_RKVDEC0_HEVC_CA 327
+#define RK3588_SRST_RKVDEC0_CORE 328
+#define RK3588_SRST_H_RKVDEC1 329
+#define RK3588_SRST_A_RKVDEC1 330
+#define RK3588_SRST_H_RKVDEC1_BIU 331
+#define RK3588_SRST_A_RKVDEC1_BIU 332
+#define RK3588_SRST_RKVDEC1_CA 333
+#define RK3588_SRST_RKVDEC1_HEVC_CA 334
+#define RK3588_SRST_RKVDEC1_CORE 335
+#define RK3588_SRST_A_USB_BIU 336
+#define RK3588_SRST_H_USB_BIU 337
+#define RK3588_SRST_A_USB3OTG0 338
+#define RK3588_SRST_A_USB3OTG1 339
+#define RK3588_SRST_H_HOST0 340
+#define RK3588_SRST_H_HOST_ARB0 341
+#define RK3588_SRST_H_HOST1 342
+#define RK3588_SRST_H_HOST_ARB1 343
+#define RK3588_SRST_A_USB_GRF 344
+#define RK3588_SRST_C_USB2P0_HOST0 345
+#define RK3588_SRST_C_USB2P0_HOST1 346
+#define RK3588_SRST_HOST_UTMI0 347
+#define RK3588_SRST_HOST_UTMI1 348
+#define RK3588_SRST_A_VDPU_BIU 349
+#define RK3588_SRST_A_VDPU_LOW_BIU 350
+#define RK3588_SRST_H_VDPU_BIU 351
+#define RK3588_SRST_A_JPEG_DECODER_BIU 352
+#define RK3588_SRST_A_VPU 353
+#define RK3588_SRST_H_VPU 354
+#define RK3588_SRST_A_JPEG_ENCODER0 355
+#define RK3588_SRST_H_JPEG_ENCODER0 356
+#define RK3588_SRST_A_JPEG_ENCODER1 357
+#define RK3588_SRST_H_JPEG_ENCODER1 358
+#define RK3588_SRST_A_JPEG_ENCODER2 359
+#define RK3588_SRST_H_JPEG_ENCODER2 360
+#define RK3588_SRST_A_JPEG_ENCODER3 361
+#define RK3588_SRST_H_JPEG_ENCODER3 362
+#define RK3588_SRST_A_JPEG_DECODER 363
+#define RK3588_SRST_H_JPEG_DECODER 364
+#define RK3588_SRST_H_IEP2P0 365
+#define RK3588_SRST_A_IEP2P0 366
+#define RK3588_SRST_IEP2P0_CORE 367
+#define RK3588_SRST_H_RGA2 368
+#define RK3588_SRST_A_RGA2 369
+#define RK3588_SRST_RGA2_CORE 370
+#define RK3588_SRST_H_RGA3_0 371
+#define RK3588_SRST_A_RGA3_0 372
+#define RK3588_SRST_RGA3_0_CORE 373
+#define RK3588_SRST_H_RKVENC0_BIU 374
+#define RK3588_SRST_A_RKVENC0_BIU 375
+#define RK3588_SRST_H_RKVENC0 376
+#define RK3588_SRST_A_RKVENC0 377
+#define RK3588_SRST_RKVENC0_CORE 378
+#define RK3588_SRST_H_RKVENC1_BIU 379
+#define RK3588_SRST_A_RKVENC1_BIU 380
+#define RK3588_SRST_H_RKVENC1 381
+#define RK3588_SRST_A_RKVENC1 382
+#define RK3588_SRST_RKVENC1_CORE 383
+#define RK3588_SRST_A_VI_BIU 384
+#define RK3588_SRST_H_VI_BIU 385
+#define RK3588_SRST_P_VI_BIU 386
+#define RK3588_SRST_D_VICAP 387
+#define RK3588_SRST_A_VICAP 388
+#define RK3588_SRST_H_VICAP 389
+#define RK3588_SRST_ISP0 390
+#define RK3588_SRST_ISP0_VICAP 391
+#define RK3588_SRST_FISHEYE0 392
+#define RK3588_SRST_FISHEYE1 393
+#define RK3588_SRST_P_CSI_HOST_0 394
+#define RK3588_SRST_P_CSI_HOST_1 395
+#define RK3588_SRST_P_CSI_HOST_2 396
+#define RK3588_SRST_P_CSI_HOST_3 397
+#define RK3588_SRST_P_CSI_HOST_4 398
+#define RK3588_SRST_P_CSI_HOST_5 399
+#define RK3588_SRST_CSIHOST0_VICAP 400
+#define RK3588_SRST_CSIHOST1_VICAP 401
+#define RK3588_SRST_CSIHOST2_VICAP 402
+#define RK3588_SRST_CSIHOST3_VICAP 403
+#define RK3588_SRST_CSIHOST4_VICAP 404
+#define RK3588_SRST_CSIHOST5_VICAP 405
+#define RK3588_SRST_CIFIN 406
+#define RK3588_SRST_A_VOP_BIU 407
+#define RK3588_SRST_A_VOP_LOW_BIU 408
+#define RK3588_SRST_H_VOP_BIU 409
+#define RK3588_SRST_P_VOP_BIU 410
+#define RK3588_SRST_H_VOP 411
+#define RK3588_SRST_A_VOP 412
+#define RK3588_SRST_D_VOP0 413
+#define RK3588_SRST_D_VOP2HDMI_BRIDGE0 414
+#define RK3588_SRST_D_VOP2HDMI_BRIDGE1 415
+#define RK3588_SRST_D_VOP1 416
+#define RK3588_SRST_D_VOP2 417
+#define RK3588_SRST_D_VOP3 418
+#define RK3588_SRST_P_VOPGRF 419
+#define RK3588_SRST_P_DSIHOST0 420
+#define RK3588_SRST_P_DSIHOST1 421
+#define RK3588_SRST_DSIHOST0 422
+#define RK3588_SRST_DSIHOST1 423
+#define RK3588_SRST_VOP_PMU 424
+#define RK3588_SRST_P_VOP_CHANNEL_BIU 425
+#define RK3588_SRST_H_VO0_BIU 426
+#define RK3588_SRST_H_VO0_S_BIU 427
+#define RK3588_SRST_P_VO0_BIU 428
+#define RK3588_SRST_P_VO0_S_BIU 429
+#define RK3588_SRST_A_HDCP0_BIU 430
+#define RK3588_SRST_P_VO0GRF 431
+#define RK3588_SRST_H_HDCP_KEY0 432
+#define RK3588_SRST_A_HDCP0 433
+#define RK3588_SRST_H_HDCP0 434
+#define RK3588_SRST_HDCP0 435
+#define RK3588_SRST_P_TRNG0 436
+#define RK3588_SRST_DP0 437
+#define RK3588_SRST_DP1 438
+#define RK3588_SRST_H_I2S4_8CH 439
+#define RK3588_SRST_M_I2S4_8CH_TX 440
+#define RK3588_SRST_H_I2S8_8CH 441
+#define RK3588_SRST_M_I2S8_8CH_TX 442
+#define RK3588_SRST_H_SPDIF2_DP0 443
+#define RK3588_SRST_M_SPDIF2_DP0 444
+#define RK3588_SRST_H_SPDIF5_DP1 445
+#define RK3588_SRST_M_SPDIF5_DP1 446
+#define RK3588_SRST_A_HDCP1_BIU 447
+#define RK3588_SRST_A_VO1_BIU 448
+#define RK3588_SRST_H_VOP1_BIU 449
+#define RK3588_SRST_H_VOP1_S_BIU 450
+#define RK3588_SRST_P_VOP1_BIU 451
+#define RK3588_SRST_P_VO1GRF 452
+#define RK3588_SRST_P_VO1_S_BIU 453
+#define RK3588_SRST_H_I2S7_8CH 454
+#define RK3588_SRST_M_I2S7_8CH_RX 455
+#define RK3588_SRST_H_HDCP_KEY1 456
+#define RK3588_SRST_A_HDCP1 457
+#define RK3588_SRST_H_HDCP1 458
+#define RK3588_SRST_HDCP1 459
+#define RK3588_SRST_P_TRNG1 460
+#define RK3588_SRST_P_HDMITX0 461
+#define RK3588_SRST_HDMITX0_REF 462
+#define RK3588_SRST_P_HDMITX1 463
+#define RK3588_SRST_HDMITX1_REF 464
+#define RK3588_SRST_A_HDMIRX 465
+#define RK3588_SRST_P_HDMIRX 466
+#define RK3588_SRST_HDMIRX_REF 467
+#define RK3588_SRST_P_EDP0 468
+#define RK3588_SRST_EDP0_24M 469
+#define RK3588_SRST_P_EDP1 470
+#define RK3588_SRST_EDP1_24M 471
+#define RK3588_SRST_M_I2S5_8CH_TX 472
+#define RK3588_SRST_H_I2S5_8CH 473
+#define RK3588_SRST_M_I2S6_8CH_TX 474
+#define RK3588_SRST_M_I2S6_8CH_RX 475
+#define RK3588_SRST_H_I2S6_8CH 476
+#define RK3588_SRST_H_SPDIF3 477
+#define RK3588_SRST_M_SPDIF3 478
+#define RK3588_SRST_H_SPDIF4 479
+#define RK3588_SRST_M_SPDIF4 480
+#define RK3588_SRST_H_SPDIFRX0 481
+#define RK3588_SRST_M_SPDIFRX0 482
+#define RK3588_SRST_H_SPDIFRX1 483
+#define RK3588_SRST_M_SPDIFRX1 484
+#define RK3588_SRST_H_SPDIFRX2 485
+#define RK3588_SRST_M_SPDIFRX2 486
+#define RK3588_SRST_LINKSYM_HDMITXPHY0 487
+#define RK3588_SRST_LINKSYM_HDMITXPHY1 488
+#define RK3588_SRST_VO1_BRIDGE0 489
+#define RK3588_SRST_VO1_BRIDGE1 490
+#define RK3588_SRST_H_I2S9_8CH 491
+#define RK3588_SRST_M_I2S9_8CH_RX 492
+#define RK3588_SRST_H_I2S10_8CH 493
+#define RK3588_SRST_M_I2S10_8CH_RX 494
+#define RK3588_SRST_P_S_HDMIRX 495
+#define RK3588_SRST_GPU 496
+#define RK3588_SRST_SYS_GPU 497
+#define RK3588_SRST_A_S_GPU_BIU 498
+#define RK3588_SRST_A_M0_GPU_BIU 499
+#define RK3588_SRST_A_M1_GPU_BIU 500
+#define RK3588_SRST_A_M2_GPU_BIU 501
+#define RK3588_SRST_A_M3_GPU_BIU 502
+#define RK3588_SRST_P_GPU_BIU 503
+#define RK3588_SRST_P_GPU_PVTM 504
+#define RK3588_SRST_GPU_PVTM 505
+#define RK3588_SRST_P_GPU_GRF 506
+#define RK3588_SRST_GPU_PVTPLL 507
+#define RK3588_SRST_GPU_JTAG 508
+#define RK3588_SRST_A_AV1_BIU 509
+#define RK3588_SRST_A_AV1 510
+#define RK3588_SRST_P_AV1_BIU 511
+#define RK3588_SRST_P_AV1 512
+#define RK3588_SRST_A_DDR_BIU 513
+#define RK3588_SRST_A_DMA2DDR 514
+#define RK3588_SRST_A_DDR_SHAREMEM 515
+#define RK3588_SRST_A_DDR_SHAREMEM_BIU 516
+#define RK3588_SRST_A_CENTER_S200_BIU 517
+#define RK3588_SRST_A_CENTER_S400_BIU 518
+#define RK3588_SRST_H_AHB2APB 519
+#define RK3588_SRST_H_CENTER_BIU 520
+#define RK3588_SRST_F_DDR_CM0_CORE 521
+#define RK3588_SRST_DDR_TIMER0 522
+#define RK3588_SRST_DDR_TIMER1 523
+#define RK3588_SRST_T_WDT_DDR 524
+#define RK3588_SRST_T_DDR_CM0_JTAG 525
+#define RK3588_SRST_P_CENTER_GRF 526
+#define RK3588_SRST_P_AHB2APB 527
+#define RK3588_SRST_P_WDT 528
+#define RK3588_SRST_P_TIMER 529
+#define RK3588_SRST_P_DMA2DDR 530
+#define RK3588_SRST_P_SHAREMEM 531
+#define RK3588_SRST_P_CENTER_BIU 532
+#define RK3588_SRST_P_CENTER_CHANNEL_BIU 533
+#define RK3588_SRST_P_USBDPGRF0 534
+#define RK3588_SRST_P_USBDPPHY0 535
+#define RK3588_SRST_P_USBDPGRF1 536
+#define RK3588_SRST_P_USBDPPHY1 537
+#define RK3588_SRST_P_HDPTX0 538
+#define RK3588_SRST_P_HDPTX1 539
+#define RK3588_SRST_P_APB2ASB_SLV_BOT_RIGHT 540
+#define RK3588_SRST_P_USB2PHY_U3_0_GRF0 541
+#define RK3588_SRST_P_USB2PHY_U3_1_GRF0 542
+#define RK3588_SRST_P_USB2PHY_U2_0_GRF0 543
+#define RK3588_SRST_P_USB2PHY_U2_1_GRF0 544
+#define RK3588_SRST_HDPTX0_ROPLL 545
+#define RK3588_SRST_HDPTX0_LCPLL 546
+#define RK3588_SRST_HDPTX0 547
+#define RK3588_SRST_HDPTX1_ROPLL 548
+#define RK3588_SRST_HDPTX1_LCPLL 549
+#define RK3588_SRST_HDPTX1 550
+#define RK3588_SRST_HDPTX0_HDMIRXPHY_SET 551
+#define RK3588_SRST_USBDP_COMBO_PHY0 552
+#define RK3588_SRST_USBDP_COMBO_PHY0_LCPLL 553
+#define RK3588_SRST_USBDP_COMBO_PHY0_ROPLL 554
+#define RK3588_SRST_USBDP_COMBO_PHY0_PCS_HS 555
+#define RK3588_SRST_USBDP_COMBO_PHY1 556
+#define RK3588_SRST_USBDP_COMBO_PHY1_LCPLL 557
+#define RK3588_SRST_USBDP_COMBO_PHY1_ROPLL 558
+#define RK3588_SRST_USBDP_COMBO_PHY1_PCS_HS 559
+#define RK3588_SRST_HDMIHDP0 560
+#define RK3588_SRST_HDMIHDP1 561
+#define RK3588_SRST_A_VO1USB_TOP_BIU 562
+#define RK3588_SRST_H_VO1USB_TOP_BIU 563
+#define RK3588_SRST_H_SDIO_BIU 564
+#define RK3588_SRST_H_SDIO 565
+#define RK3588_SRST_SDIO 566
+#define RK3588_SRST_H_RGA3_BIU 567
+#define RK3588_SRST_A_RGA3_BIU 568
+#define RK3588_SRST_H_RGA3_1 569
+#define RK3588_SRST_A_RGA3_1 570
+#define RK3588_SRST_RGA3_1_CORE 571
+#define RK3588_SRST_REF_PIPE_PHY0 572
+#define RK3588_SRST_REF_PIPE_PHY1 573
+#define RK3588_SRST_REF_PIPE_PHY2 574
+#define RK3588_SRST_P_PHPTOP_CRU 575
+#define RK3588_SRST_P_PCIE2_GRF0 576
+#define RK3588_SRST_P_PCIE2_GRF1 577
+#define RK3588_SRST_P_PCIE2_GRF2 578
+#define RK3588_SRST_P_PCIE2_PHY0 579
+#define RK3588_SRST_P_PCIE2_PHY1 580
+#define RK3588_SRST_P_PCIE2_PHY2 581
+#define RK3588_SRST_P_PCIE3_PHY 582
+#define RK3588_SRST_P_APB2ASB_SLV_CHIP_TOP 583
+#define RK3588_SRST_PCIE30_PHY 584
+#define RK3588_SRST_H_PMU1_BIU 585
+#define RK3588_SRST_P_PMU1_BIU 586
+#define RK3588_SRST_H_PMU_CM0_BIU 587
+#define RK3588_SRST_F_PMU_CM0_CORE 588
+#define RK3588_SRST_T_PMU1_CM0_JTAG 589
+#define RK3588_SRST_DDR_FAIL_SAFE 590
+#define RK3588_SRST_P_CRU_PMU1 591
+#define RK3588_SRST_P_PMU1_GRF 592
+#define RK3588_SRST_P_PMU1_IOC 593
+#define RK3588_SRST_P_PMU1WDT 594
+#define RK3588_SRST_T_PMU1WDT 595
+#define RK3588_SRST_P_PMU1TIMER 596
+#define RK3588_SRST_PMU1TIMER0 597
+#define RK3588_SRST_PMU1TIMER1 598
+#define RK3588_SRST_P_PMU1PWM 599
+#define RK3588_SRST_PMU1PWM 600
+#define RK3588_SRST_P_I2C0 601
+#define RK3588_SRST_I2C0 602
+#define RK3588_SRST_S_UART0 603
+#define RK3588_SRST_P_UART0 604
+#define RK3588_SRST_H_I2S1_8CH 605
+#define RK3588_SRST_M_I2S1_8CH_TX 606
+#define RK3588_SRST_M_I2S1_8CH_RX 607
+#define RK3588_SRST_H_PDM0 608
+#define RK3588_SRST_PDM0 609
+#define RK3588_SRST_H_VAD 610
+#define RK3588_SRST_HDPTX0_INIT 611
+#define RK3588_SRST_HDPTX0_CMN 612
+#define RK3588_SRST_HDPTX0_LANE 613
+#define RK3588_SRST_HDPTX1_INIT 614
+#define RK3588_SRST_HDPTX1_CMN 615
+#define RK3588_SRST_HDPTX1_LANE 616
+#define RK3588_SRST_M_MIPI_DCPHY0 617
+#define RK3588_SRST_S_MIPI_DCPHY0 618
+#define RK3588_SRST_M_MIPI_DCPHY1 619
+#define RK3588_SRST_S_MIPI_DCPHY1 620
+#define RK3588_SRST_OTGPHY_U3_0 621
+#define RK3588_SRST_OTGPHY_U3_1 622
+#define RK3588_SRST_OTGPHY_U2_0 623
+#define RK3588_SRST_OTGPHY_U2_1 624
+#define RK3588_SRST_P_PMU0GRF 625
+#define RK3588_SRST_P_PMU0IOC 626
+#define RK3588_SRST_P_GPIO0 627
+#define RK3588_SRST_GPIO0 628
+#define RK3588_SRST_A_SECURE_NS_BIU 629
+#define RK3588_SRST_H_SECURE_NS_BIU 630
+#define RK3588_SRST_A_SECURE_S_BIU 631
+#define RK3588_SRST_H_SECURE_S_BIU 632
+#define RK3588_SRST_P_SECURE_S_BIU 633
+#define RK3588_SRST_CRYPTO_CORE 634
+#define RK3588_SRST_CRYPTO_PKA 635
+#define RK3588_SRST_CRYPTO_RNG 636
+#define RK3588_SRST_A_CRYPTO 637
+#define RK3588_SRST_H_CRYPTO 638
+#define RK3588_SRST_KEYLADDER_CORE 639
+#define RK3588_SRST_KEYLADDER_RNG 640
+#define RK3588_SRST_A_KEYLADDER 641
+#define RK3588_SRST_H_KEYLADDER 642
+#define RK3588_SRST_P_OTPC_S 643
+#define RK3588_SRST_OTPC_S 644
+#define RK3588_SRST_WDT_S 645
+#define RK3588_SRST_T_WDT_S 646
+#define RK3588_SRST_H_BOOTROM 647
+#define RK3588_SRST_A_DCF 648
+#define RK3588_SRST_P_DCF 649
+#define RK3588_SRST_H_BOOTROM_NS 650
+#define RK3588_SRST_P_KEYLADDER 651
+#define RK3588_SRST_H_TRNG_S 652
+#define RK3588_SRST_H_TRNG_NS 653
+#define RK3588_SRST_D_SDMMC_BUFFER 654
+#define RK3588_SRST_H_SDMMC 655
+#define RK3588_SRST_H_SDMMC_BUFFER 656
+#define RK3588_SRST_SDMMC 657
+#define RK3588_SRST_P_TRNG_CHK 658
+#define RK3588_SRST_TRNG_S 659
+
#endif /* _#define RK3588_CRU_H_ */
diff --git a/sys/arch/arm/rockchip/rk_cru.c b/sys/arch/arm/rockchip/rk_cru.c
index 644c55eab462..9ce426358ab0 100644
--- a/sys/arch/arm/rockchip/rk_cru.c
+++ b/sys/arch/arm/rockchip/rk_cru.c
@@ -46,10 +46,25 @@ __KERNEL_RCSID(0, "$NetBSD: rk_cru.c,v 1.10 2022/09/18 21:33:57 ryo Exp $");
static void *
rk_cru_reset_acquire(device_t dev, const void *data, size_t len)
{
+ struct rk_cru_softc * const sc = device_private(dev);
+ uint32_t reset_id;
+
if (len != 4)
return NULL;
- return (void *)(uintptr_t)be32dec(data);
+ reset_id = be32dec(data);
+
+ if (sc->sc_srst_lut != NULL) {
+ if (reset_id < sc->sc_nsrst) {
+ reset_id = sc->sc_srst_lut[reset_id];
+ } else {
+ aprint_error_dev(sc->sc_dev,
+ "softreset not found: %" PRIu32 "\n", reset_id);
+ return NULL;
+ }
+ }
+
+ return (void *)(uintptr_t)reset_id;
}
static void
diff --git a/sys/arch/arm/rockchip/rk_cru.h b/sys/arch/arm/rockchip/rk_cru.h
index f6f2189b1be5..134b202f1a8a 100644
--- a/sys/arch/arm/rockchip/rk_cru.h
+++ b/sys/arch/arm/rockchip/rk_cru.h
@@ -454,6 +454,9 @@ struct rk_cru_softc {
struct rk_cru_clk *sc_clks;
u_int sc_nclks;
+ uint32_t *sc_srst_lut;
+ u_int sc_nsrst;
+
bus_size_t sc_grf_soc_status; /* for PLL lock */
bus_size_t sc_softrst_base;
};
>Release-Note:
>Audit-Trail:
Responsible-Changed-From-To: port-evbarm-maintainer->tnn
Responsible-Changed-By: tnn@NetBSD.org
Responsible-Changed-When: Thu, 18 Apr 2024 07:29:10 +0000
Responsible-Changed-Why:
take
>Unformatted:
(Contact us)
$NetBSD: query-full-pr,v 1.47 2022/09/11 19:34:41 kim Exp $
$NetBSD: gnats_config.sh,v 1.9 2014/08/02 14:16:04 spz Exp $
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The NetBSD Foundation, Inc. ALL RIGHTS RESERVED.
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