NetBSD Problem Report #13350
Received: (qmail 20432 invoked from network); 1 Jul 2001 13:10:10 -0000
Message-Id: <Pine.SOL.4.33.0107011407300.5439-100000@virgo.cus.cam.ac.uk>
Date: Sun, 1 Jul 2001 14:13:00 +0100 (BST)
From: Ben Harris <bjh21@netbsd.org>
Sender: Ben Harris <bjh21@cus.cam.ac.uk>
To: <gnats-bugs@gnats.netbsd.org>
Subject: Patch for Connect32 SCSI card
>Number: 13350
>Category: port-acorn32
>Synopsis: Patch for Connect32 SCSI card
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: port-acorn32-maintainer
>State: open
>Class: change-request
>Submitter-Id: net
>Arrival-Date: Sun Jul 01 13:11:00 +0000 2001
>Closed-Date:
>Last-Modified: Mon Feb 28 14:58:33 +0000 2011
>Originator: Ben Harris
>Release: 1.5.1
>Organization:
>Environment:
>Description:
From port-arm32:
| From: Jan-Uwe Finck <jufi@nerdnet.de>
| Date: Sun Jul 01 13:32:02 BST 2001
| Lines: 18
|
| Yesterday I talked to Leo Smiers who has built a patch for the
| Connect32 card several months ago and he sent it to me.
|
| As he left the NetBSD camp now, I put the patch on my homepage and
| hope someone will fit it into -current.
| Of course I'm willing to help testing it.
|
| As the software is several months old it has to be trimmed to fit into
| current.
[ The patch moves cosc over to using the MI ncr53c9x driver ]
>How-To-Repeat:
>Fix:
http://www.nerdnet.de/connect32.tgz
>Release-Note:
>Audit-Trail:
From: Mike Pumford <mpumford@black-star.demon.co.uk>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-acorn32/13350
Date: Fri, 05 Apr 2002 18:57:00 +0100
This is a multipart MIME message.
--==_Exmh_17188663090
Content-Type: text/plain; charset=us-ascii
Attached is a version of this patch which will work with 1.5ZA current (should
be okay up to 1.5ZC)
Mike
--==_Exmh_17188663090
Content-Type: application/x-patch ; name="cosc.patch"
Content-Description: cosc.patch
Content-Transfer-Encoding: quoted-printable
Content-Disposition: attachment; filename="cosc.patch"
Index: podulebus/cosc.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/syssrc/sys/arch/acorn32/podulebus/cosc.c,v
retrieving revision 1.3
diff -u -r1.3 cosc.c
--- cosc.c 2001/11/27 00:53:12 1.3
+++ cosc.c 2002/03/29 14:50:16
@@ -1,7 +1,10 @@
-/* $NetBSD: cosc.c,v 1.3 2001/11/27 00:53:12 thorpej Exp $ */
+/* $NetBSD$ */
=
/*
- * Copyright (c) 1996 Mark Brinicombe
+ * Copyright (c) 1997 Michael L. Hitch
+ * Copyright (c) 1995 Daniel Widenfalk
+ * Copyright (c) 1994 Christian E. Hopps
+ * Copyright (c) 1982, 1990 The Regents of the University of California.=
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -14,450 +17,691 @@
* documentation and/or other materials provided with the distributio=
n.
* 3. All advertising materials mentioning features or use of this softw=
are
* must display the following acknowledgement:
- * This product includes software developed by Mark Brinicombe
- * for the NetBSD Project.
+ * This product includes software developed by Daniel Widenfalk
+ * and Michael L. Hitch.
* 4. Neither the name of the University nor the names of its contributo=
rs
* may be used to endorse or promote products derived from this softw=
are
* without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRAN=
TIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIME=
D.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, =
BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF =
USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY=
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE=
OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' A=
ND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PU=
RPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIA=
BLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUE=
NTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOO=
DS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)=
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, S=
TRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY=
WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY O=
F
+ * SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
*
- * from: asc.c,v 1.8 1996/06/12 20:46:58 mark Exp
+ * This software contains code contributed to The NetBSD Foundation
+ * by Mark Brinicombe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in th=
e
+ * documentation and/or other materials provided with the distributio=
n.
+ * 3. All advertising materials mentioning features or use of this softw=
are
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBU=
TORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT L=
IMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTI=
CULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBU=
TORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, O=
R
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSIN=
ESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER =
IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWIS=
E)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED O=
F THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * SCSI driver for the Connect32 SCSI II interface
+ *
+ * from: amiga/dev/flsc.c,v 1.21 1998/07/04 22:18:16
*/
=
/*
- * Driver for the MCS Connect 32 SCSI 2 card with AM53C94 SCSI controlle=
r.
- *
- * Thanks to Mike <mcsmike@knipp.de> at MCS for loaning a card.
- * Thanks to Andreas Gandor <andi@knipp.de> for some technical informati=
on
+ * Forces the interface to work in polling mode. Currently necessary
+ * as there is no information on how to do DMA based transfers on this
+ * card.
*/
+#define COSC_POLL
+
+/* Define this flag to enable verbose debugging of this driver. */
+/*#define COSC_DEBUG*/
=
+#include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
+#include <sys/errno.h>
+#include <sys/ioctl.h>
#include <sys/device.h>
+#include <sys/buf.h>
+#include <sys/proc.h>
+#include <sys/user.h>
+#include <sys/queue.h>
+
#include <dev/scsipi/scsi_all.h>
#include <dev/scsipi/scsipi_all.h>
#include <dev/scsipi/scsiconf.h>
+#include <dev/scsipi/scsi_message.h>
+
#include <machine/bootconfig.h>
+#include <machine/cpu.h>
+#include <machine/param.h>
#include <machine/io.h>
-#include <machine/intr.h>
-#include <arm/arm32/katelib.h>
+
+#include <dev/ic/ncr53c9xreg.h>
+#include <dev/ic/ncr53c9xvar.h>
+
#include <acorn32/podulebus/podulebus.h>
-#include <acorn32/podulebus/escreg.h>
-#include <acorn32/podulebus/escvar.h>
-#include <acorn32/podulebus/coscreg.h>
-#include <acorn32/podulebus/coscvar.h>
#include <dev/podulebus/podules.h>
+#include <acorn32/podulebus/coscvar.h>
+#include <acorn32/podulebus/coscreg.h>
=
-void coscattach __P((struct device *, struct device *, void *));
-int coscmatch __P((struct device *, struct cfdata *, void *));
-void cosc_scsi_request __P((struct scsipi_channel *,
- scsipi_adapter_req_t, void *));
+void coscattach __P((struct device *, struct device *, void *));
+int coscmatch __P((struct device *, struct cfdata *, void *));
=
+/* Linkup to the rest of the kernel */
struct cfattach cosc_ca =3D {
sizeof(struct cosc_softc), coscmatch, coscattach
};
=
-int cosc_intr __P((void *arg));
-int cosc_setup_dma __P((struct esc_softc *sc, void *ptr, int len,
- int mode));
-int cosc_build_dma_chain __P((struct esc_softc *sc,
- struct esc_dma_chain *chain, void *p, int l));
-int cosc_need_bump __P((struct esc_softc *sc, void *ptr, int len));
-
-void cosc_led __P((struct esc_softc *sc, int mode));
=
-#if COSC_POLL > 0
-int cosc_poll =3D 1;
+/*
+ * Functions and the switch for the MI code.
+ */
+u_char cosc_read_reg __P((struct ncr53c9x_softc *, int));
+void cosc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
+int cosc_dma_isintr __P((struct ncr53c9x_softc *));
+void cosc_dma_reset __P((struct ncr53c9x_softc *));
+int cosc_dma_intr __P((struct ncr53c9x_softc *));
+int cosc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, size_t *, in=
t, size_t *));
+void cosc_dma_go __P((struct ncr53c9x_softc *));
+void cosc_dma_stop __P((struct ncr53c9x_softc *));
+int cosc_dma_isactive __P((struct ncr53c9x_softc *));
+#ifdef COSC_DEBUG
+int cosc_intr __P((void *arg));
#endif
+static int cosc_get_firmware_version(bus_space_tag_t othert,
+ bus_space_handle_t otherh);
+
+struct ncr53c9x_glue cosc_glue =3D {
+ cosc_read_reg,
+ cosc_write_reg,
+ cosc_dma_isintr,
+ cosc_dma_reset,
+ cosc_dma_intr,
+ cosc_dma_setup,
+ cosc_dma_go,
+ cosc_dma_stop,
+ cosc_dma_isactive,
+ NULL,
+};
=
+/*extern int ncr53c9x_debug;*/
=
+/*
+ * if we are a Connect32 card
+ */
int
-coscmatch(pdp, cf, auxp)
- struct device *pdp;
- struct cfdata *cf;
- void *auxp;
+coscmatch(parent, cf, aux)
+ struct device *parent;
+ struct cfdata *cf;
+ void *aux;
{
- struct podule_attach_args *pa =3D (struct podule_attach_args *)auxp;
+ struct podule_attach_args *pa =3D (struct podule_attach_args *)aux;
=
/* Look for the card */
-
- if (matchpodule(pa, MANUFACTURER_MCS, PODULE_MCS_SCSI, -1) !=3D 0)
+ if (matchpodule(pa, MANUFACTURER_MCS, PODULE_MCS_SCSI, -1) !=3D 0) {
return(1);
-
+ }
/* Old versions of the ROM on this card could have the wrong ID */
-
- if (matchpodule(pa, MANUFACTURER_ACORN, PODULE_ACORN_SCSI, -1) =3D=3D 0=
)
+ if (matchpodule(pa, MANUFACTURER_ACORN, PODULE_ACORN_SCSI, -1) =3D=3D 0=
) {
return(0);
-
- if (strncmp(pa->pa_podule->description, "MCS", 3) !=3D 0)
+ }
+ if (strncmp(pa->pa_podule->description, "MCS", 3) !=3D 0) {
return(0);
+ }
=
+#ifdef COSC_DEBUG
+ /* Set Debug */
+ ncr53c9x_debug =3D NCR_SHOWDMA;
+#endif
+
return(1);
}
-
-static int dummy[6];
=
+/*
+ * Attach this instance, and then all the sub-devices
+ */
void
-coscattach(pdp, dp, auxp)
- struct device *pdp, *dp;
- void *auxp;
-{
- struct cosc_softc *sc =3D (struct cosc_softc *)dp;
- struct podule_attach_args *pa;
- cosc_regmap_p rp =3D &sc->sc_regmap;
- vu_char *esc;
+coscattach(parent, self, aux)
+ struct device *parent, *self;
+ void *aux;
+{
+ struct podule_attach_args *pa =3D (struct podule_attach_args *)aux;
+ struct cosc_softc *cosc =3D (void *)self;
+ struct ncr53c9x_softc *sc =3D &cosc->sc_ncr53c9x;
+ bus_space_handle_t bus_config_h;
+ bus_space_handle_t bus_other_h;
+ unsigned int iobase;
=
- pa =3D (struct podule_attach_args *)auxp;
-
- if (pa->pa_podule_number =3D=3D -1)
+ if (pa->pa_podule_number =3D=3D -1) {
panic("Podule has disappeared !");
-
- sc->sc_podule_number =3D pa->pa_podule_number;
- sc->sc_podule =3D pa->pa_podule;
- podules[sc->sc_podule_number].attached =3D 1;
-
- printf(":");
+ }
=
if (pa->pa_podule->manufacturer =3D=3D MANUFACTURER_ACORN
- && pa->pa_podule->product =3D=3D PODULE_ACORN_SCSI)
+ && pa->pa_podule->product =3D=3D PODULE_ACORN_SCSI) {
printf(" Faulty expansion card identity\n");
+ }
=
- sc->sc_iobase =3D (vu_char *)sc->sc_podule->fast_base;
+ /*
+ * Set up the glue for MI code early; we use some of it here.
+ */
+ sc->sc_glue =3D &cosc_glue;
=
- /* Select page zero (so we can see the config info) */
+ /*
+ * Set up the register pointers
+ */
+ iobase =3D pa->pa_podule->fast_base;
+ /* setup bus space cookie (shift for registers) */
+ cosc->sc_tag_store =3D *pa->pa_iot;
+ cosc->sc_tag =3D &(cosc->sc_tag_store);
+ cosc->sc_tag->bs_cookie =3D (void *) COSC_REGSHIFT;
+ if (bus_space_map(cosc->sc_tag,(iobase + COSC_ESCOFFSET_BASE),
+ COSC_REGSIZE, 0, &cosc->sc_regh)) {
+ printf ("%s: Cannot map register space\n", self->dv_xname);
+ return;
+ }
+ if (bus_space_map(cosc->sc_tag,iobase + COSC_CONFIG_BASE,
+ COSC_CONFIG_SIZE, 0,&bus_config_h)) {
+ printf ("%s: Cannot map config register space\n", =
+ self->dv_xname);
+ /* XXX unmap esc space */
+ return;
+ }
+ if (bus_space_map(cosc->sc_tag,iobase + COSC_OTHER_BASE,
+ COSC_OTHER_SIZE, 0, &bus_other_h)) {
+ printf ("%s: Cannot map config register space\n", =
+ self->dv_xname);
+ /* XXX unmap esc space and config base */
+ return;
+ }
=
- sc->sc_iobase[COSC_PAGE_REGISTER] =3D 0;
+ sc->sc_freq =3D 40; /* Clocked at 40Mhz */
=
- rp->chipreset =3D (vu_char *)&dummy[0];
- rp->inten =3D (vu_char *)&dummy[1];
- rp->status =3D (vu_char *)&dummy[2];
- rp->term =3D &sc->sc_iobase[COSC_TERMINATION_CONTROL];
- rp->led =3D (vu_char *)&dummy[4];
- esc =3D &sc->sc_iobase[COSC_ESCOFFSET_BASE];
-
- rp->esc.esc_tc_low =3D &esc[COSC_ESCOFFSET_TCL];
- rp->esc.esc_tc_mid =3D &esc[COSC_ESCOFFSET_TCM];
- rp->esc.esc_fifo =3D &esc[COSC_ESCOFFSET_FIFO];
- rp->esc.esc_command =3D &esc[COSC_ESCOFFSET_COMMAND];
- rp->esc.esc_dest_id =3D &esc[COSC_ESCOFFSET_DESTID];
- rp->esc.esc_timeout =3D &esc[COSC_ESCOFFSET_TIMEOUT];
- rp->esc.esc_syncper =3D &esc[COSC_ESCOFFSET_PERIOD];
- rp->esc.esc_syncoff =3D &esc[COSC_ESCOFFSET_OFFSET];
- rp->esc.esc_config1 =3D &esc[COSC_ESCOFFSET_CONFIG1];
- rp->esc.esc_clkconv =3D &esc[COSC_ESCOFFSET_CLOCKCONV];
- rp->esc.esc_test =3D &esc[COSC_ESCOFFSET_TEST];
- rp->esc.esc_config2 =3D &esc[COSC_ESCOFFSET_CONFIG2];
- rp->esc.esc_config3 =3D &esc[COSC_ESCOFFSET_CONFIG3];
- rp->esc.esc_config4 =3D &esc[COSC_ESCOFFSET_CONFIG4];
- rp->esc.esc_tc_high =3D &esc[COSC_ESCOFFSET_TCH];
- rp->esc.esc_fifo_bot =3D &esc[COSC_ESCOFFSET_FIFOBOTTOM];
-
- *rp->esc.esc_command =3D ESC_CMD_RESET_CHIP;
- delay(1000);
- *rp->esc.esc_command =3D ESC_CMD_NOP;
-
- /* See if we recognise the controller */
-
- switch (*rp->esc.esc_tc_high) {
- case 0x12:
- printf(" AM53CF94");
- break;
- default:
- printf(" Unknown controller (%02x)", *rp->esc.esc_tc_high);
- break;
- }
+ /* Select page zero (so we can see the config info) */
+ bus_space_write_1(cosc->sc_tag,bus_other_h,COSC_PAGE_REGISTER, 0);
=
+ sc->sc_id =3D 7;
+ /* Provide an override for the host id */
+ (void)get_bootconf_option(boot_args, "cosc.hostid", BOOTOPT_TYPE_INT, &=
sc->sc_id);
+ =
/* Set termination power */
-
- if (sc->sc_iobase[COSC_CONFIG_TERMINATION] & COSC_CONFIG_TERMINATION_ON=
) {
- printf(" termpwr on");
- sc->sc_iobase[COSC_TERMINATION_CONTROL] =3D COSC_TERMINATION_ON;
+ if (bus_space_read_1(cosc->sc_tag,bus_config_h,
+ COSC_CONFIG_TERMINATION) &
+ COSC_CONFIG_TERMINATION_ON) {
+ printf(" termpwr=3Don");
+ bus_space_write_1(cosc->sc_tag,bus_other_h,
+ COSC_TERMINATION_CONTROL,
+ COSC_TERMINATION_ON);
} else {
- printf(" termpwr off");
- sc->sc_iobase[COSC_TERMINATION_CONTROL] =3D COSC_TERMINATION_OFF;
+ printf(" termpwr=3Doff");
+ bus_space_write_1(cosc->sc_tag,bus_other_h,
+ COSC_TERMINATION_CONTROL,
+ COSC_TERMINATION_OFF);
}
+ =
=
- /* Don't know what this is for */
-
- {
- int byte;
- int loop;
+ /* Get firmware version */
+ printf (" firmware=3D1.%02x",
+ cosc_get_firmware_version(cosc->sc_tag,bus_other_h));
=
- byte =3D sc->sc_iobase[COSC_REGISTER_01];
- byte =3D 0;
- for (loop =3D 0; loop < 8; ++loop) {
- if (sc->sc_iobase[COSC_REGISTER_00] & 0x01)
- byte |=3D (1 << loop);
- }
- printf(" byte=3D%02x", byte);
- }
=
+ =
/*
- * Control register 4 is an AMD special (not on FAS216)
- *
- * The powerdown and glitch eater facilities could be useful
- * Use the podule configuration for this register
+ * It is necessary to try to load the 2nd config register here,
+ * to find out what rev the flsc chip is, else the flsc_reset
+ * will not set up the defaults correctly.
*/
-
- sc->sc_softc.sc_config4 =3D sc->sc_iobase[COSC_CONFIG_CONTROL_REG4];
+ sc->sc_cfg1 =3D sc->sc_id | NCRCFG1_PARENB;
+ sc->sc_cfg2 =3D NCRCFG2_SCSI2 | NCRCFG2_FE;
+ sc->sc_cfg3 =3D 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
=
- sc->sc_softc.sc_esc =3D (esc_regmap_p)rp;
-/* sc->sc_softc.sc_spec =3D &sc->sc_specific;*/
+ sc->sc_rev =3D NCR_VARIANT_NCR53C94;
=
- sc->sc_softc.sc_led =3D cosc_led;
- sc->sc_softc.sc_setup_dma =3D cosc_setup_dma;
- sc->sc_softc.sc_build_dma_chain =3D cosc_build_dma_chain;
- sc->sc_softc.sc_need_bump =3D cosc_need_bump;
+ /*
+ * This is the value used to start sync negotiations
+ * Note that the NCR register "SYNCTP" is programmed
+ * in "clocks per byte", and has a minimum value of 4.
+ * The SCSI period used in negotiation is one-fourth
+ * of the time (in nanoseconds) needed to transfer one byte.
+ * Since the chip's clock is given in MHz, we have the following
+ * formula: 4 * period =3D (1000 / freq) * 4
+ */
+/* sc->sc_minsync =3D 1000 / sc->sc_freq;*/
+ sc->sc_minsync =3D 0;
=
- sc->sc_softc.sc_clock_freq =3D 40; /* Connect32 runs at 40MHz */
- sc->sc_softc.sc_timeout =3D 250; /* Set default timeout to 250ms =
*/
- sc->sc_softc.sc_config_flags =3D ESC_NO_DMA;
- sc->sc_softc.sc_host_id =3D sc->sc_iobase[COSC_CONFIG_CONTROL_REG1=
] & ESC_DEST_ID_MASK;
+ /* Really no limit, but since we want to fit into the TCR... */
+ sc->sc_maxxfer =3D 64 * 1024;
+#ifdef COSC_DEBUG
+ ncr53c9x_debug |=3D NCR_SHOWDMA; =
+#endif
=
- printf(" hostid=3D%d", sc->sc_softc.sc_host_id);
+#ifndef COSC_POLL
+ /*
+ * Configure interrupts.
+ */
+#ifdef COSC_DEBUG
+ cosc->sc_ih.ih_func =3D (void *)cosc_intr;
+#else
+ cosc->sc_ih.ih_func =3D (void *)ncr53c9x_intr;
+#endif
+ cosc->sc_ih.ih_arg =3D sc;
+ cosc->sc_ih.ih_level =3D IPL_BIO;
+ cosc->sc_ih.ih_name =3D "cosc";
+ cosc->sc_ih.ih_maskaddr =3D pa->pa_podule->irq_addr;
+ cosc->sc_ih.ih_maskbits =3D pa->pa_podule->irq_mask;
=
-#if COSC_POLL > 0
- if (boot_args)
- get_bootconf_option(boot_args, "coscpoll",
- BOOTOPT_TYPE_BOOLEAN, &cosc_poll);
+ if (irq_claim(IRQ_PODULE, &cosc->sc_ih)) {
+ panic("%s: Cannot install IRQ handler\n", self->dv_xname);
+ }
=
- if (cosc_poll)
- printf(" polling");
+ /* Enable interrupts */
+ *cosc->sc_inten =3D COSC_INTERRUPTS_ON;
+ sc->sc_features =3D 0;
+ printf(" mode=3Dinterrupts");
+
+#else
+ /* Disable interrupts and flag no-interrupt mode */
+ printf(" mode=3Dpolling");
+ sc->sc_adapter.adapt_flags |=3D SCSIPI_ADAPT_POLL_ONLY;
+ =
#endif
+ printf(" dma_channel=3D%d", pa->pa_podule->dma_channel);
+
+ /*
+ * Now try to attach all the sub-devices
+ */
+ sc->sc_adapter.adapt_minphys =3D minphys;
+//#ifdef COSC_POLL
+// sc->sc_adapter.adapt_request =3D cosc_scsipi_request;
+//#else
+ sc->sc_adapter.adapt_request =3D ncr53c9x_scsipi_request;
+//#endif
+
+ ncr53c9x_attach(sc);
+}
+
+static int cosc_get_firmware_version(othert,otherh)
+ bus_space_tag_t othert;
+ bus_space_handle_t otherh;
+{
+ int byte;
+ int loop;
+ =
+ /* read register 1 to start reading the firmware version */
+ bus_space_read_1(othert, otherh,
+ COSC_REGISTER_01);
+
+ byte =3D 0;
+ /* read the firmware version */
+ for (loop =3D 0; loop < 8; ++loop) {
+ if (bus_space_read_1(othert, otherh,
+ COSC_REGISTER_00) & 0x01)
+ byte |=3D (1 << loop);
+ }
+ return byte;
+}
=
- sc->sc_softc.sc_bump_sz =3D NBPG;
- sc->sc_softc.sc_bump_pa =3D 0x0;
=
- escinitialize((struct esc_softc *)sc);
+/*
+ * Glue functions.
+ */
=
- sc->sc_softc.sc_adapter.adapt_dev =3D &sc->sc_softc.sc_dev;
- sc->sc_softc.sc_adapter.adapt_nchannels =3D 1;
- sc->sc_softc.sc_adapter.adapt_openings =3D 7;
- sc->sc_softc.sc_adapter.adapt_max_periph =3D 1;
- sc->sc_softc.sc_adapter.adapt_ioctl =3D NULL;
- sc->sc_softc.sc_adapter.adapt_minphys =3D esc_minphys;
- sc->sc_softc.sc_adapter.adapt_request =3D cosc_scsi_request;
+u_char
+cosc_read_reg(sc, reg)
+ struct ncr53c9x_softc *sc;
+ int reg;
+{
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
+ return bus_space_read_1(cosc->sc_tag,cosc->sc_regh,reg);
+/* return cosc->sc_reg[reg * COSC_FAS_REG_SPACING]; */
+}
=
- sc->sc_softc.sc_channel.chan_adapter =3D &sc->sc_softc.sc_adapter;
- sc->sc_softc.sc_channel.chan_bustype =3D &scsi_bustype;
- sc->sc_softc.sc_channel.chan_channel =3D 0;
- sc->sc_softc.sc_channel.chan_ntargets =3D 8;
- sc->sc_softc.sc_channel.chan_nluns =3D 8; =
- sc->sc_softc.sc_channel.chan_id =3D sc->sc_softc.sc_host_id;
+void
+cosc_write_reg(sc, reg, val)
+ struct ncr53c9x_softc *sc;
+ int reg;
+ u_char val;
+{
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
+ struct ncr53c9x_tinfo *ti;
+ u_char v =3D val;
+
+ if (cosc->sc_piomode =3D=3D SC_PIOMODE_PIO && reg =3D=3D NCR_CMD &&
+ v =3D=3D (NCRCMD_TRANS|NCRCMD_DMA)) {
+ v =3D NCRCMD_TRANS;
+ }
+ /*
+ * Can't do synchronous transfers in SCSI_POLL mode:
+ * If starting SCSI_POLL command, clear defer sync negotiation
+ * by clearing the T_NEGOTIATE flag. If starting SCSI_POLL and
+ * the device is currently running synchronous, force another
+ * T_NEGOTIATE with 0 offset.
+ */
+ if (reg =3D=3D NCR_SELID) {
+ ti =3D &sc->sc_tinfo[
+ sc->sc_nexus->xs->xs_periph->periph_target];
+ if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) {
+ if (ti->flags & T_SYNCMODE) {
+ ti->flags ^=3D T_SYNCMODE | T_NEGOTIATE;
+ } else if (ti->flags & T_NEGOTIATE) {
+ ti->flags ^=3D T_NEGOTIATE | T_SYNCHOFF;
+ /* save T_NEGOTIATE in private flags? */
+ }
+ } else {
+ /*
+ * If we haven't attempted sync negotiation yet,
+ * do it now.
+ */
+ if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) =3D=3D
+ T_SYNCHOFF &&
+ sc->sc_minsync !=3D 0) { /* XXX */
+ ti->flags ^=3D T_NEGOTIATE | T_SYNCHOFF;
+ }
+ }
+ }
+ if (reg =3D=3D NCR_CMD && v =3D=3D NCRCMD_SETATN &&
+ sc->sc_flags & NCR_SYNCHNEGO &&
+ sc->sc_nexus->xs->xs_control & XS_CTL_POLL) {
+ ti =3D &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
+ ti->offset =3D 0;
+ }
+ bus_space_write_1(cosc->sc_tag,cosc->sc_regh,reg,v);
+/* cosc->sc_reg[reg * COSC_FAS_REG_SPACING] =3D v; */
+}
=
- /* initialise the card */
-#if 0
- *rp->inten =3D (COSC_POLL?0:1);
- *rp->led =3D 0;
-#endif
+int
+cosc_dma_isintr(sc)
+ struct ncr53c9x_softc *sc;
+{
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
=
- sc->sc_softc.sc_ih.ih_func =3D cosc_intr;
- sc->sc_softc.sc_ih.ih_arg =3D &sc->sc_softc;
- sc->sc_softc.sc_ih.ih_level =3D IPL_BIO;
- sc->sc_softc.sc_ih.ih_name =3D "scsi: cosc";
- sc->sc_softc.sc_ih.ih_maskaddr =3D sc->sc_podule->irq_addr;
- sc->sc_softc.sc_ih.ih_maskbits =3D sc->sc_podule->irq_mask;
=
-#if COSC_POLL > 0
- if (!cosc_poll)
+ if (bus_space_read_1(cosc->sc_tag,cosc->sc_regh,
+ NCR_STAT) & NCRSTAT_INT) {
+#ifdef COSC_DEBUG
+ printf("cosc_dma_isintr: cosc interrupt\n");
#endif
- {
- evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
- dp->dv_xname, "intr");
- sc->sc_ih =3D podulebus_irq_establish(pa->pa_ih, IPL_BIO,
- cosc_intr, sc, &sc->sc_intrcnt);
- if (sc->sc_ih =3D=3D NULL)
- panic("%s: Cannot install IRQ handler\n",
- dp->dv_xname);
+ return 1;
}
=
- printf("\n");
-
- /* attach all scsi units on us */
- config_found(dp, &sc->sc_softc.sc_channel, scsiprint);
+ return 0;
}
=
=
-/* Turn on/off led */
-
void
-cosc_led(sc, mode)
- struct esc_softc *sc;
- int mode;
+cosc_dma_reset(sc)
+ struct ncr53c9x_softc *sc;
{
- cosc_regmap_p rp;
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
+ struct ncr53c9x_tinfo *ti;
=
- rp =3D (cosc_regmap_p)sc->sc_esc;
-
- if (mode) {
- sc->sc_led_status++;
+ if (sc->sc_nexus) {
+ ti =3D &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
} else {
- if (sc->sc_led_status)
- sc->sc_led_status--;
+ ti =3D &sc->sc_tinfo[1]; /* XXX */
+ }
+#ifdef COSC_DEBUG
+ if (cosc->sc_active) {
+ printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x",
+ *cosc->sc_dmaaddr, cosc->sc_dmasize,
+ bus_space_read_1(cosc->sc_tag,cosc->sc_regh,NCR_STAT),
+ ti->flags, ti->offset, ti->period, =
+ bus_space_read_1(cosc->sc_tag, cosc->sc_regh,NCR_FFLAG)
+ );
+ printf(" intr %x\n", =
+ bus_space_read_1(cosc->sc_tag, cosc->sc_regh,
+ NCR_INTR));
}
-/* *rp->led =3D (sc->sc_led_status?1:0);*/
+#endif
+ cosc->sc_active =3D 0;
}
=
-
int
-cosc_intr(arg)
- void *arg;
+cosc_dma_intr(sc)
+ struct ncr53c9x_softc *sc;
{
- struct esc_softc *dev =3D arg;
- cosc_regmap_p rp;
- int quickints;
-
- rp =3D (cosc_regmap_p)dev->sc_esc;
-
- printf("cosc_intr:%08x %02x\n", (u_int)rp->esc.esc_status, *rp->esc.esc=
_status);
-
- if (*rp->esc.esc_status & ESC_STAT_INTERRUPT_PENDING) {
- quickints =3D 16;
- do {
- dev->sc_status =3D *rp->esc.esc_status;
- dev->sc_interrupt =3D *rp->esc.esc_interrupt;
- =
- if (dev->sc_interrupt & ESC_INT_RESELECTED) {
- dev->sc_resel[0] =3D *rp->esc.esc_fifo;
- dev->sc_resel[1] =3D *rp->esc.esc_fifo;
- }
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
+ u_char *p;
+ u_int coscphase, coscstat, coscintr;
+ int cnt;
+
+ NCR_DMA(("cosc_dma_intr: piomode %d cnt %d int %x stat %x fifo %d ",
+ cosc->sc_piomode, cosc->sc_dmasize, sc->sc_espintr,
+ sc->sc_espstat,
+ bus_space_read_1(cosc->sc_tag, cosc->sc_regh,NCR_FFLAG) &
+ NCRFIFO_FF));
+
+ if (cosc->sc_active =3D=3D 0) {
+#ifdef COSC_DEBUG
+ printf("cosc_intr--inactive DMA\n");
+#endif
+ return -1;
+ }
=
- escintr(dev);
+ /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */
+ if (cosc->sc_piomode =3D=3D SC_PIOMODE_DMA) {
+ /* DMA */
+ panic("cosc_dma_intr");
+ }
+ /* PIO */
=
- } while((*rp->esc.esc_status & ESC_STAT_INTERRUPT_PENDING)
- && --quickints);
+ if ((sc->sc_espintr & NCRINTR_BS) =3D=3D 0) {
+ cosc->sc_active =3D 0;
+ cosc->sc_piomode =3D SC_PIOMODE_DMA;
+ NCR_DMA(("no NCRINTR_BS\n"));
+ return 0;
}
=
- return(0); /* Pass interrupt on down the chain */
-}
+ cnt =3D cosc->sc_dmasize;
=
+#ifdef COSC_DEBUG
+ if (cnt =3D=3D 0) {
+ printf("data interrupt, but no count left.");
+ }
+#endif
=
-/* Load transfer address into dma register */
+ p =3D *cosc->sc_dmaaddr;
+ coscphase =3D sc->sc_phase;
+ coscstat =3D (u_int) sc->sc_espstat;
+ coscintr =3D (u_int) sc->sc_espintr;
+ NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n",
+ cnt, cosc->sc_datain, coscphase, coscstat, coscintr)); =
+ do {
+ if (cosc->sc_datain) {
+ *p++ =3D bus_space_read_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_FIFO);
+ /* *p++ =3D *fiforeg; */
+ cnt--;
+ if (coscphase =3D=3D DATA_IN_PHASE) {
+ bus_space_write_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_CMD, =
+ NCRCMD_TRANS);
+ } else {
+ cosc->sc_active =3D 0;
+ }
+ } else {
+ NCR_DMA(("cosc_dma_intr: PIO out- phase %d cnt %d active %d\n",
+ coscphase, cnt, cosc->sc_active));
+ if ((coscphase =3D=3D DATA_OUT_PHASE) || =
+ (coscphase =3D=3D MESSAGE_OUT_PHASE)) {
+ int n =3D 16;
+ n -=3D bus_space_read_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_FFLAG) & NCRFIFO_FF;
+ if (n > cnt) {
+ n =3D cnt;
+ }
+ cnt -=3D n;
+ bus_space_write_multi_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_FIFO,p,
+ n);
+ p +=3D n;
+ bus_space_write_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_CMD,NCRCMD_TRANS);
+ } else {
+ cosc->sc_active =3D 0;
+ }
+ }
=
-void
-cosc_set_dma_adr(sc, ptr)
- struct esc_softc *sc;
- void *ptr;
-{
- printf("cosc_set_dma_adr(sc =3D 0x%08x, ptr =3D 0x%08x)\n", (u_int)sc, =
(u_int)ptr);
- return;
-}
+ if (cosc->sc_active && cnt) {
+ while (!(bus_space_read_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_STAT) & 0x80));
+ coscstat =3D bus_space_read_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_STAT);
+ coscintr =3D bus_space_read_1(cosc->sc_tag,
+ cosc->sc_regh,
+ NCR_INTR);
+ coscphase =3D (coscintr & NCRINTR_DIS) ? /* Disconnected */ BUSFREE_P=
HASE : coscstat & PHASE_MASK;
+ }
+ } while (cnt && cosc->sc_active && (coscintr & NCRINTR_BS));
+#ifdef COSC_DEBUG
+ if (cosc->sc_dmasize < 8 && cnt) {
+ printf("cosc_dma_intr: short transfer: dmasize %d cnt %d\n", cosc->sc_=
dmasize, cnt);
+ }
+#endif
+ NCR_DMA(("cosc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x int=
r %x\n",
+ *cosc->sc_pdmalen, cosc->sc_dmasize, cnt, coscphase, coscstat, cosc=
intr));
+ sc->sc_phase =3D coscphase;
+ sc->sc_espstat =3D (u_char) coscstat;
+ sc->sc_espintr =3D (u_char) coscintr;
+ *cosc->sc_dmaaddr =3D p;
+ *cosc->sc_pdmalen -=3D cosc->sc_dmasize - cnt;
+ cosc->sc_dmasize =3D cnt;
=
+ if (*cosc->sc_pdmalen =3D=3D 0) {
+ sc->sc_espstat |=3D NCRSTAT_TC;
+ }
+ return 0;
+}
=
-/* Set DMA transfer counter */
+int
+cosc_dma_setup(sc, addr, len, datain, dmasize)
+ struct ncr53c9x_softc *sc;
+ caddr_t *addr;
+ size_t *len;
+ int datain;
+ size_t *dmasize;
+{
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
+
+ cosc->sc_dmaaddr =3D addr;
+ cosc->sc_pdmalen =3D len;
+ cosc->sc_datain =3D datain;
+ cosc->sc_dmasize =3D *dmasize;
+
+ /* XXX force PIO/POLL */
+ cosc->sc_piomode =3D SC_PIOMODE_PIO;
+
+ /* IF pio or POLL */
+ if (cosc->sc_piomode =3D=3D SC_PIOMODE_PIO) {
+ *dmasize =3D cosc->sc_dmasize;
+ NCR_DMA(("cosc_dma_setup: PIO %p/%d [%d]\n", *addr,
+ cosc->sc_dmasize, *len));
+ if (datain =3D=3D 0) {
+ int n;
+ n =3D cosc->sc_dmasize;
+ if (n > 16) {
+ n =3D 16;
+ }
+ bus_space_write_multi_1(cosc->sc_tag, cosc->sc_regh,
+ NCR_FIFO,
+ *cosc->sc_dmaaddr,n);
+ (*cosc->sc_pdmalen) -=3D n;
+ (*cosc->sc_dmaaddr) +=3D n;
+ cosc->sc_dmasize -=3D n;
+ =
+ }
+ return 0;
+ }
+ /* XXX TODO Support DMA */
+ return 0;
+}
=
void
-cosc_set_dma_tc(sc, len)
- struct esc_softc *sc;
- unsigned int len;
+cosc_dma_go(sc)
+ struct ncr53c9x_softc *sc;
{
- printf("cosc_set_dma_tc(sc, len =3D 0x%08x)", len);
-
- /* Set the transfer size on the SCSI controller */
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
=
- *sc->sc_esc->esc_tc_low =3D len; len >>=3D 8;
- *sc->sc_esc->esc_tc_mid =3D len; len >>=3D 8;
- *sc->sc_esc->esc_tc_high =3D len;
+ NCR_DMA(("cosc_dma_go: datain %d size %d\n", cosc->sc_datain, cosc->sc_=
dmasize));
+ if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) {
+ cosc->sc_active =3D 1;
+ return;
+ } else if (cosc->sc_piomode =3D=3D SC_PIOMODE_DMA) {
+ /* DMA */
+ panic("cosc_dma_go");
+ } else {
+ cosc->sc_active =3D 1;
+ }
}
=
-
-/* Set DMA mode */
-
void
-cosc_set_dma_mode(sc, mode)
- struct esc_softc *sc;
- int mode;
-{
- printf("cosc_set_dma_mode(sc, mode =3D %d)", mode);
-}
-
-
-/* Initialize DMA for transfer */
-
-int
-cosc_setup_dma(sc, ptr, len, mode)
- struct esc_softc *sc;
- void *ptr;
- int len;
- int mode;
+cosc_dma_stop(sc)
+ struct ncr53c9x_softc *sc;
{
-/* printf("cosc_setup_dma(sc, ptr =3D 0x%08x, len =3D 0x%08x, mode =3D 0=
x%08x)\n", (u_int)ptr, len, mode);*/
- return(0);
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
=
+ cosc->sc_piomode =3D SC_PIOMODE_DMA;
}
=
-
-/* Check if address and len is ok for DMA transfer */
-
int
-cosc_need_bump(sc, ptr, len)
- struct esc_softc *sc;
- void *ptr;
- int len;
+cosc_dma_isactive(sc)
+ struct ncr53c9x_softc *sc;
{
- int p;
-
- p =3D (int)ptr & 0x03;
-
- if (p) {
- p =3D 4-p;
- =
- if (len < 256)
- p =3D len;
- }
+ struct cosc_softc *cosc =3D (struct cosc_softc *)sc;
=
- return(p);
+ return cosc->sc_active;
}
-
-
-/* Interrupt driven routines */
=
+/* Only used for debugging */
+#ifdef COSC_DEBUG
+/* Only used to cleanup trace output as interrupt is shared */
int
-cosc_build_dma_chain(sc, chain, p, l)
- struct esc_softc *sc;
- struct esc_dma_chain *chain;
- void *p;
- int l;
-{
- printf("cosc_build_dma_chain()\n");
- return(0);
-}
-
-
-void
-cosc_scsi_request(chan, req, arg)
- struct scsipi_channel *chan;
- scsipi_adapter_req_t req;
+cosc_intr(arg)
void *arg;
{
- struct scsipi_xfer *xs;
+ struct ncr53c9x_softc *sc =3D arg;
=
- switch (req) {
- case ADAPTER_REQ_RUN_XFER:
- xs =3D arg;
-
-#if COSC_POLL > 0
- if (cosc_poll)
- xs->xs_control |=3D XS_CTL_POLL;
-#endif
-#if 0
- if (periph->periph_lun =3D=3D 0)
- printf("id=3D%d lun=3D%d cmdlen=3D%d datalen=3D%d opcode=3D%02x flags=3D=
%08x status=3D%02x blk=3D%02x %02x\n",
- xs->xs_periph->periph_target, xs->xs_periph->periph_lun, xs->cmdle=
n, xs->datalen, xs->cmd->opcode,
- xs->xs_control, xs->status, xs->cmd->bytes[0], xs->cmd->bytes[1]);=
-#endif
- default:
+ if (cosc_dma_isintr(sc)) {
+ return(ncr53c9x_intr(sc));
}
- esc_scsi_request(chan, req, arg);
+ return(0);
}
+#endif
Index: podulebus/coscreg.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/syssrc/sys/arch/acorn32/podulebus/coscreg.h,v
retrieving revision 1.1
diff -u -r1.1 coscreg.h
--- coscreg.h 2001/10/05 22:27:54 1.1
+++ coscreg.h 2002/03/29 14:50:16
@@ -1,7 +1,7 @@
-/* $NetBSD: coscreg.h,v 1.1 2001/10/05 22:27:54 reinoud Exp $ */
+/* $NetBSD$ */
=
/*
- * Copyright (c) 1996 Mark Brinicombe
+ * Copyright (c) 1997 Michael L. Hitch.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -14,11 +14,10 @@
* documentation and/or other materials provided with the distributio=
n.
* 3. All advertising materials mentioning features or use of this softw=
are
* must display the following acknowledgement:
- * This product includes software developed by Mark Brinicombe
- * for the NetBSD Project.
- * 4. Neither the name of the University nor the names of its contributo=
rs
- * may be used to endorse or promote products derived from this softw=
are
- * without specific prior written permission.
+ * This product includes software developed for the NetBSD Project
+ * by Michael L. Hitch.
+ * 4. The name of the author may not be used to endorse or promote produ=
cts
+ * derived from this software without specific prior written permissi=
on.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRAN=
TIES
@@ -30,82 +29,65 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE=
OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
*/
=
/*
- * Termination and DMA enable registers provided by
- * Andreas Gandor <andi@knipp.de>
+ * Ported to arm32 for the MCS Connect 32 by Leo Smiers.
+ * Converted to bus space and the new scsipi layer by Mike Pumford.
*/
-
-#ifndef _COSCREG_H_
-#define _COSCREG_H_
-
-#include <acorn32/podulebus/escvar.h>
=
-typedef volatile unsigned short vu_short;
+#define SC_PIOMODE_DMA 0
+#define SC_PIOMODE_PIO 1
=
-typedef struct cosc_regmap {
- esc_regmap_t esc;
- vu_char *chipreset;
- vu_char *inten;
- vu_char *status;
- vu_char *term;
- vu_char *led;
-} cosc_regmap_t;
-typedef cosc_regmap_t *cosc_regmap_p;
-
-/*
-#define COSC_CONTROL_CHIPRESET
-#define COSC_CONTROL_INTEN
-#define COSC_STATUS
-#define COSC_CONTROL_LED
-*/
+#define COSC_CONFIG_BASE 0x0ff0
+#define COSC_CONFIG_SIZE 0x80
=
-#define COSC_CONFIG_CONTROL_REG1 0x0ff0
+#define COSC_CONFIG_CONTROL_REG1 0x00
#define COSC_CONFIG_CONTROL_REG1_MASK 0x97
-#define COSC_CONFIG_CONTROL_REG2 0x0ff4
+
+#define COSC_CONFIG_CONTROL_REG2 0x01
#define COSC_CONFIG_CONTROL_REG2_MASK 0x07
-#define COSC_CONFIG_CONTROL_REG3 0x0ff8
+
+#define COSC_CONFIG_CONTROL_REG3 0x02
#define COSC_CONFIG_CONTROL_REG3_MASK 0x83
-#define COSC_CONFIG_CONTROL_REG4 0x0ffc
+
+#define COSC_CONFIG_CONTROL_REG4 0x03
#define COSC_CONFIG_CONTROL_REG4_MASK 0xec
-#define COSC_CONFIG_TERMINATION 0x1000
+
+#define COSC_CONFIG_TERMINATION 0x04
#define COSC_CONFIG_TERMINATION_ON 0x01
-#define COSC_CONFIG_FIRST_SCANNED 0x1040 /* Used by RiscOS */
-#define COSC_CONFIG_INC_FURTHER_PARTS 0x1048 /* Used by RiscOS */
-#define COSC_CONFIG_SYNCH_MODE 0x1050
+
+#define COSC_CONFIG_FIRST_SCANNED 0x14 /* Used by RiscOS */
+#define COSC_CONFIG_INC_FURTHER_PARTS 0x16 /* Used by RiscOS */
+#define COSC_CONFIG_SYNCH_MODE 0x18
#define COSC_CONFIG_SYNCH_MODE_ON 0x01
-#define COSC_CONFIG_SHUTDOWN 0x1054 /* Used by RiscOS */
+
+#define COSC_CONFIG_SHUTDOWN 0x19 /* Used by RiscOS */
#define COSC_CONFIG_SHUTDOWN_SPINDOWN 0x01 /* Used by RiscOS */
#define COSC_CONFIG_SHUTDOWN_EJECT 0x02 /* Used by RiscOS */
-#define COSC_CONFIG_DELAY_REMOVABLE 0x105c /* Used by RiscOS */
-#define COSC_CONFIG_DELAY_HARDDISC 0x1060 /* Used by RiscOS */
-#define COSC_CONFIG_DELAY_BOOT 0x1064 /* Used by RiscOS */
-#define COSC_CONFIG_CDROM 0x1068 /* Used by RiscOS */
+
+#define COSC_CONFIG_DELAY_REMOVABLE 0x1b /* Used by RiscOS */
+#define COSC_CONFIG_DELAY_HARDDISC 0x1c /* Used by RiscOS */
+#define COSC_CONFIG_DELAY_BOOT 0x1d /* Used by RiscOS */
+#define COSC_CONFIG_CDROM 0x1e /* Used by RiscOS */
+
+#define COSC_OTHER_BASE 0x2600
+#define COSC_OTHER_SIZE 0x400
=
-#define COSC_TERMINATION_CONTROL 0x2600
+#define COSC_TERMINATION_CONTROL 0x00
#define COSC_TERMINATION_ON 0x00
#define COSC_TERMINATION_OFF 0x01
-#define COSC_REGISTER_00 0x2800
-#define COSC_REGISTER_01 0x2a00
-#define COSC_PAGE_REGISTER 0x3000
=
-#define COSC_ESCOFFSET_BASE 0x3c00
-#define COSC_ESCOFFSET_TCL 0x0000
-#define COSC_ESCOFFSET_TCM 0x0004
-#define COSC_ESCOFFSET_FIFO 0x0008
-#define COSC_ESCOFFSET_COMMAND 0x000c
-#define COSC_ESCOFFSET_DESTID 0x0010
-#define COSC_ESCOFFSET_TIMEOUT 0x0014
-#define COSC_ESCOFFSET_PERIOD 0x0018
-#define COSC_ESCOFFSET_OFFSET 0x001c
-#define COSC_ESCOFFSET_CONFIG1 0x0020
-#define COSC_ESCOFFSET_CLOCKCONV 0x0024
-#define COSC_ESCOFFSET_TEST 0x0028
-#define COSC_ESCOFFSET_CONFIG2 0x002c
-#define COSC_ESCOFFSET_CONFIG3 0x0030
-#define COSC_ESCOFFSET_CONFIG4 0x0034
-#define COSC_ESCOFFSET_TCH 0x0038
-#define COSC_ESCOFFSET_FIFOBOTTOM 0x003c
+#define COSC_REGISTER_00 0x080
+
+#define COSC_REGISTER_01 0x100
=
-#endif /* _COSCREG_H_ */
+#define COSC_PAGE_REGISTER 0x400
+
+
+
+#define COSC_ESCOFFSET_BASE 0x3c00
+#define COSC_FAS_REG_SPACING 4
+#define COSC_REGSHIFT 2
+#define COSC_REGSIZE 16
Index: podulebus/coscvar.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/syssrc/sys/arch/acorn32/podulebus/coscvar.h,v
retrieving revision 1.1
diff -u -r1.1 coscvar.h
--- coscvar.h 2001/10/05 22:27:55 1.1
+++ coscvar.h 2002/03/29 14:50:16
@@ -1,7 +1,8 @@
-/* $NetBSD: coscvar.h,v 1.1 2001/10/05 22:27:55 reinoud Exp $ */
+/* $NetBSD$ */
=
/*
- * Copyright (c) 1996 Mark Brinicombe
+ * Copyright (c) 1997 Michael L. Hitch.
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -13,10 +14,10 @@
* documentation and/or other materials provided with the distributio=
n.
* 3. All advertising materials mentioning features or use of this softw=
are
* must display the following acknowledgement:
- * This product includes software developed by Mark Brinicombe
- * for the NetBSD Project.
+ * This product includes software developed for the NetBSD Project
+ * by Michael L. Hitch.
* 4. The name of the author may not be used to endorse or promote produ=
cts
- * derived from this software without specific prior written permissi=
on
+ * derived from this software without specific prior written permissi=
on.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRAN=
TIES
@@ -30,22 +31,21 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
=
-#ifndef _COSCVAR_H_
-#define _COSCVAR_H_
+struct cosc_softc {
+ struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
=
-#include <acorn32/podulebus/escvar.h>
-#include <acorn32/podulebus/coscreg.h>
-
-#define COSC_POLL 1
-
-struct cosc_softc {
- struct esc_softc sc_softc;
- cosc_regmap_t sc_regmap;
- vu_char *sc_iobase;
- podule_t *sc_podule;
- int sc_podule_number;
- void *sc_ih;
- struct evcnt sc_intrcnt;
+ irqhandler_t sc_ih; /* Interrupt chain struct */
+ /* Bus space tag and handle for device registers */
+ struct bus_space sc_tag_store; /* patched tag */
+ struct bus_space *sc_tag; /* patched tag */
+ =
+ bus_space_handle_t sc_regh; /* handle for NCR registers */
+ =
+ int sc_active; /* Pseudo-DMA state vars */
+ int sc_piomode;
+ int sc_datain;
+ size_t sc_dmasize;
+ char **sc_dmaaddr;
+ size_t *sc_pdmalen;
};
=
-#endif /* _COCVAR_H_ */
Index: conf/files.acorn32
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/syssrc/sys/arch/acorn32/conf/files.acorn32,v
retrieving revision 1.8
diff -u -r1.8 files.acorn32
--- files.acorn32 2002/02/11 21:48:48 1.8
+++ files.acorn32 2002/03/29 14:50:16
@@ -228,7 +228,7 @@
file arch/acorn32/podulebus/esc.c esc
=
# Connect32 specific layer for esc
-device cosc: scsi, esc
+device cosc: scsi, ncr53c9x
attach cosc at podulebus
file arch/acorn32/podulebus/cosc.c cosc
=
--==_Exmh_17188663090--
Responsible-Changed-From-To: port-arm32-maintainer->port-acorn32-maintainer
Responsible-Changed-By: chris
Responsible-Changed-When: Sun Aug 4 12:17:28 PDT 2002
Responsible-Changed-Why:
This is an acorn32 bug, not an arm32 bug.
Responsible-Changed-From-To: port-acorn32-maintainer->bjh21
Responsible-Changed-By: reinoud
Responsible-Changed-When: Thu Aug 5 17:30:51 UTC 2004
Responsible-Changed-Why:
I dont have objections to it but i can't test it due to lack of hardware...
Responsible-Changed-From-To: bjh21->port-acorn32-maintainer
Responsible-Changed-By: wiz@NetBSD.org
Responsible-Changed-When: Mon, 28 Feb 2011 14:58:33 +0000
Responsible-Changed-Why:
Reset responsible field for retired developer.
>Unformatted:
(Contact us)
$NetBSD: query-full-pr,v 1.39 2013/11/01 18:47:49 spz Exp $
$NetBSD: gnats_config.sh,v 1.8 2006/05/07 09:23:38 tsutsui Exp $
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