NetBSD Problem Report #40213

From ryoh@bonnie.jaist.ac.jp  Wed Dec 17 20:36:36 2008
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Date: Thu, 18 Dec 2008 05:36:32 +0900 (JST)
From: Ryo HAYASAKA <ryoh@jaist.ac.jp>
Reply-To: ryoh@jaist.ac.jp
To: gnats-bugs@gnats.NetBSD.org
Subject: my i386 machine can't boot because of tsc
X-Send-Pr-Version: 3.95

>Number:         40213
>Category:       kern
>Synopsis:       my i386 machine can't boot because of tsc
>Confidential:   no
>Severity:       serious
>Priority:       high
>Responsible:    kern-bug-people
>State:          closed
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Wed Dec 17 20:40:00 +0000 2008
>Closed-Date:    Sun Dec 28 10:58:53 +0000 2008
>Last-Modified:  Mon Feb 02 03:10:03 +0000 2009
>Originator:     Ryo HAYASAKA
>Release:        NetBSD 5.99.5
>Organization:
Japan Advanced Institute of Science and Technology (JAIST)
>Environment:
System: NetBSD bonnie.jaist.ac.jp 5.99.5 NetBSD 5.99.5 (BONNIE) #14: Thu Dec 18 04:44:56 JST 2008 root@bonnie.jaist.ac.jp:/usr/src/sys/arch/i386/compile/BONNIE i386
Architecture: i386
Machine: i386
>Description:
The kernel using after revision 1.21 of /sys/arch/x86/x86/tsc.c can't
boot up.  The machine is rebooted as soon as probing timecounter in the
bootstrap process.

The revision 1.20 of it is OK.

The following is the part of boot messages of my machine when the
revision 1.20 of tsc.c is used:

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 5.99.5 (BONNIE) #14: Thu Dec 18 04:44:56 JST 2008
	root@bonnie.jaist.ac.jp:/usr/src/sys/arch/i386/compile/BONNIE
total memory = 2047 MB
avail memory = 2003 MB
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
MICRO-STAR INTERNATIONAL CO., LTD MS-7125 (3.0)
mainbus0 (root)
cpu0 at mainbus0 apid 0: AMD 686-class, 2411MHz, id 0x20fb1
cpu1 at mainbus0 apid 1: AMD 686-class, 2411MHz, id 0x20fb1
ioapic0 at mainbus0 apid 2: pa 0xfec00000, version 11, 24 pins
acpi0 at mainbus0: Intel ACPICA 20080321
acpi0: X/RSDT: OemId <Nvidia,AWRDACPI,42302e31>, AslId <AWRD,00000000>
acpi0: SCI interrupting at int 9
acpi0: fixed-feature power button present
timecounter: Timecounter "ACPI-Fast" frequency 3579545 Hz quality 1000
ACPI-Fast 24-bit timer
acpibut0 at acpi0 (PWRB, PNP0C0C): ACPI Power Button
attimer1 at acpi0 (TMR, PNP0100): AT Timer
attimer1: io 0x40-0x43 irq 0
...

>How-To-Repeat:

>Fix:


>Release-Note:

>Audit-Trail:
From: Andrew Doran <ad@netbsd.org>
To: gnats-bugs@NetBSD.org
Cc: 
Subject: Re: kern/40213: my i386 machine can't boot because of tsc
Date: Wed, 17 Dec 2008 21:13:13 +0000

 On Wed, Dec 17, 2008 at 08:40:00PM +0000, Ryo HAYASAKA wrote:

 > The kernel using after revision 1.21 of /sys/arch/x86/x86/tsc.c can't
 > boot up.  The machine is rebooted as soon as probing timecounter in the
 > bootstrap process.
 > 
 > The revision 1.20 of it is OK.

 I think I see why. There are two versions of the atomic_cas_64() routine.
 One works on the i486 and the other is for the Pentium and later. We patch
 the kernel text when secondary CPUs are started. There problems with this:

 - The i486 routine is the default but is not MP-atomic.
 - The i486 routine enables interrupts unconditionally.
 - The Pentium routine needs to be patched in much earlier if available.
   Unlike other patches, this one is not a performance optimization but
   is a requirement for the system to function properly.

 Thanks,
 Andrew

From: Andrew Doran <ad@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/40213 CVS commit: src
Date: Fri, 19 Dec 2008 11:21:25 +0000 (UTC)

 Module Name:	src
 Committed By:	ad
 Date:		Fri Dec 19 11:21:25 UTC 2008

 Modified Files:
 	src/common/lib/libc/arch/i386/atomic: atomic.S
 	src/sys/arch/x86/include: cpufunc.h
 	src/sys/arch/x86/x86: cpu.c identcpu.c patch.c

 Log Message:
 PR kern/40213 my i386 machine can't boot because of tsc

 - Patch in atomic_cas_64() twice. The first patch is early and makes it
   the MP-atomic version available if we have cmpxchg8b. The second patch
   strips the lock prefix if ncpu==1.

 - Fix the i486 atomic_cas_64() to not unconditionally enable interrupts.


 To generate a diff of this commit:
 cvs rdiff -r1.13 -r1.14 src/common/lib/libc/arch/i386/atomic/atomic.S
 cvs rdiff -r1.8 -r1.9 src/sys/arch/x86/include/cpufunc.h
 cvs rdiff -r1.59 -r1.60 src/sys/arch/x86/x86/cpu.c
 cvs rdiff -r1.11 -r1.12 src/sys/arch/x86/x86/identcpu.c
 cvs rdiff -r1.14 -r1.15 src/sys/arch/x86/x86/patch.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

State-Changed-From-To: open->feedback
State-Changed-By: ad@NetBSD.org
State-Changed-When: Fri, 19 Dec 2008 11:32:05 +0000
State-Changed-Why:
I think it should be fixed, can you test it?


From: Ryo HAYASAKA <ryoh@jaist.ac.jp>
To: gnats-bugs@NetBSD.org
Cc: 
Subject: Re: kern/40213 (my i386 machine can't boot because of tsc)
Date: Thu, 25 Dec 2008 04:44:48 +0900 (JST)

 In the message on Fri, 19 Dec 2008 11:32:06 +0000 (UTC),
 ad@NetBSD.org wrote:

 > I think it should be fixed, can you test it?

 The problem is fixed.  Thanks!

 --
 Ryo HAYASAKA <ryoh@jaist.ac.jp>
 Japan Advanced Institute of Science and Technology (JAIST)

State-Changed-From-To: feedback->closed
State-Changed-By: ad@NetBSD.org
State-Changed-When: Sun, 28 Dec 2008 10:58:53 +0000
State-Changed-Why:
submitter confirms fixed


From: Soren Jacobsen <snj@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/40213 CVS commit: [netbsd-5] src
Date: Mon,  2 Feb 2009 03:06:13 +0000 (UTC)

 Module Name:	src
 Committed By:	snj
 Date:		Mon Feb  2 03:06:13 UTC 2009

 Modified Files:
 	src/common/lib/libc/arch/i386/atomic [netbsd-5]: atomic.S
 	src/sys/arch/x86/include [netbsd-5]: cpufunc.h
 	src/sys/arch/x86/x86 [netbsd-5]: cpu.c identcpu.c patch.c

 Log Message:
 Pull up following revision(s) (requested by ad in ticket #343):
 	common/lib/libc/arch/i386/atomic/atomic.S: revision 1.14
 	sys/arch/x86/include/cpufunc.h: revision 1.9
 	sys/arch/x86/x86/identcpu.c: revision 1.12
 	sys/arch/x86/x86/cpu.c: revision 1.60
 	sys/arch/x86/x86/patch.c: revision 1.15
 PR kern/40213 my i386 machine can't boot because of tsc
 - Patch in atomic_cas_64() twice. The first patch is early and makes it
   the MP-atomic version available if we have cmpxchg8b. The second patch
   strips the lock prefix if ncpu==1.
 - Fix the i486 atomic_cas_64() to not unconditionally enable interrupts.


 To generate a diff of this commit:
 cvs rdiff -r1.13 -r1.13.4.1 src/common/lib/libc/arch/i386/atomic/atomic.S
 cvs rdiff -r1.8 -r1.8.10.1 src/sys/arch/x86/include/cpufunc.h
 cvs rdiff -r1.57.4.1 -r1.57.4.2 src/sys/arch/x86/x86/cpu.c
 cvs rdiff -r1.10 -r1.10.4.1 src/sys/arch/x86/x86/identcpu.c
 cvs rdiff -r1.14 -r1.14.4.1 src/sys/arch/x86/x86/patch.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

>Unformatted:

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