NetBSD Problem Report #41267
From www@NetBSD.org Wed Apr 22 12:47:39 2009
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Message-Id: <20090422124739.29CD463B8A5@www.NetBSD.org>
Date: Wed, 22 Apr 2009 12:47:39 +0000 (UTC)
From: vezhlys@gmail.com
Reply-To: vezhlys@gmail.com
To: gnats-bugs@NetBSD.org
Subject: 5.0 RC4 does not detect second CPU in VIA VT-310DP motherboard
X-Send-Pr-Version: www-1.0
>Number: 41267
>Category: port-i386
>Synopsis: 5.0 RC4 does not detect second CPU in VIA VT-310DP motherboard
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: port-i386-maintainer
>State: closed
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Wed Apr 22 12:50:01 +0000 2009
>Closed-Date: Fri Jan 04 10:10:26 +0000 2013
>Last-Modified: Fri Jan 04 10:10:26 +0000 2013
>Originator: Andrius Varanavičius
>Release: NetBSD 5.0 RC4
>Organization:
>Environment:
NetBSD agraphic-nas.VIDANDRIUS 5.0_RC4 NetBSD 5.0_RC4 (GENERIC) #0: Wed Apr 15 12:24:14 UTC 2009 builds@b6.netbsd.org:/home/builds/ab/netbsd-5-0-RC4/i386/200904142015Z-obj/home/builds/ab/netbsd-5-0-RC4/src/sys/arch/i386/compile/GENERIC i386
>Description:
I have VIA VT-310DP motherboard with two VIA Eden-N CPUs. Whenever I try to boot NetBSD 5.0 RC4 it hangs when detecting second CPU (during NetBSD installation too):
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 5.0_RC4 (GENERIC) #0: Wed Apr 15 12:24:14 UTC 2009
builds@b6.netbsd.org:/home/builds/ab/netbsd-5-0-RC4/i386/200904142015Z-obj/home/builds/ab/netbsd-5-0-RC4/src/sys/arch/i386/compile/GENERIC
total memory = 2029 MB
avail memory = 1982 MB
VIA Technologies, Inc. CN400-8237 ( )
mainbus0 (root)
cpu0 at mainbus0 apid 0: IDT/VIA 686-class, 531MHz, id 0x69a
cpu0 at mainbus0 apid 1
If I am booting system without SMP and ACPI support (boot netbsd -12) it loads ok, however, only one cpu is enabled. I had NetBSD 4.0.1 earlier with custom compiled MP kernel and it worked ok with both CPUs.
>How-To-Repeat:
Boot system with SMP support.
>Fix:
Boot without SMP support
>Release-Note:
>Audit-Trail:
From: Jukka Ruohonen <jruohonen@iki.fi>
To: gnats-bugs@NetBSD.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA VT-310DP motherboard
Date: Wed, 4 Aug 2010 12:19:36 +0300
On Wed, Apr 22, 2009 at 12:50:01PM +0000, vezhlys@gmail.com wrote:
> If I am booting system without SMP and ACPI support (boot netbsd -12) it
> loads ok, however, only one cpu is enabled. I had NetBSD 4.0.1 earlier
> with custom compiled MP kernel and it worked ok with both CPUs.
Can you post the acpidump(8) output?
Note that it does not matter from which operating system you issue the
command.
From: Andrius V <vezhlys@gmail.com>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Wed, 11 Aug 2010 09:35:45 +0300
Hello,
I've just read your reply. I'll do this in two days.
Regards,
Andrius V
On Wed, Aug 4, 2010 at 2:10 PM, Jukka Ruohonen <jruohonen@iki.fi> wrote:
> The following reply was made to PR port-i386/41267; it has been noted by =
GNATS.
>
> From: Jukka Ruohonen <jruohonen@iki.fi>
> To: gnats-bugs@NetBSD.org
> Cc:
> Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA V=
T-310DP motherboard
> Date: Wed, 4 Aug 2010 12:19:36 +0300
>
> =C2=A0On Wed, Apr 22, 2009 at 12:50:01PM +0000, vezhlys@gmail.com wrote:
> =C2=A0> If I am booting system without SMP and ACPI support (boot netbsd =
-12) it
> =C2=A0> loads ok, however, only one cpu is enabled. =C2=A0I had NetBSD 4.=
0.1 earlier
> =C2=A0> with custom compiled MP kernel and it worked ok with both CPUs.
>
> =C2=A0Can you post the acpidump(8) output?
>
> =C2=A0Note that it does not matter from which operating system you issue =
the
> =C2=A0command.
>
>
From: David Holland <dholland-bugs@netbsd.org>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard]
Date: Sun, 15 Aug 2010 04:01:12 +0000
Didn't get sent to gnats. (gnats mail should be sent to gnats-bugs)
------
From: Andrius V <vezhlys@gmail.com>
To: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Sat, 14 Aug 2010 15:20:13 +0300
acpidump -dt:
/*
RSD PTR: OEM=CN400, ACPI_Rev=1.0x (0)
RSDT=0x7ede3040, cksum=208
*/
/*
RSDT: Length=44, Revision=1, Checksum=96,
OEMID=CN400, OEM Table ID=AWRDACPI, OEM Revision=0x42302e31,
Creator ID=AWRD, Creator Revision=0x0
Entries={ 0x7ede30c0, 0x7ede7f80 }
*/
/*
FACP: Length=116, Revision=1, Checksum=103,
OEMID=CN400, OEM Table ID=AWRDACPI, OEM Revision=0x42302e31,
Creator ID=AWRD, Creator Revision=0x0
FACS=0x7ede0000, DSDT=0x7ede3180
INT_MODEL=APIC
Preferred_PM_Profile=Unspecified (0)
SCI_INT=9
SMI_CMD=0x42f, ACPI_ENABLE=0xa1, ACPI_DISABLE=0xa0, S4BIOS_REQ=0x0
PSTATE_CNT=0x0
PM1a_EVT_BLK=0x400-0x403
PM1a_CNT_BLK=0x404-0x405
PM_TMR_BLK=0x408-0x40b
GPE0_BLK=0x420-0x423
P_LVL2_LAT=80 us, P_LVL3_LAT=800 us
FLUSH_SIZE=0, FLUSH_STRIDE=0
DUTY_OFFSET=0, DUTY_WIDTH=1
DAY_ALRM=125, MON_ALRM=126, CENTURY=50
IAPC_BOOT_ARCH=
Flags={WBINVD,C1_SUPPORTED,SLEEP_BUTTON,S4_RTC_WAKE,RESET_REGISTER}
RESET_REG=0x00000000:0[0] (Memory), RESET_VALUE=0
*/
/*
FACS: Length=64, HwSig=0x00000000, Firm_Wake_Vec=0x00000000
Global_Lock=
Flags=
Version=0
*/
/*
DSDT: Length=19852, Revision=1, Checksum=179,
OEMID=CN400, OEM Table ID=AWRDACPI, OEM Revision=0x1000,
Creator ID=MSFT, Creator Revision=0x100000e
*/
/*
APIC: Length=104, Revision=1, Checksum=207,
OEMID=CN400, OEM Table ID=AWRDACPI, OEM Revision=0x42302e31,
Creator ID=AWRD, Creator Revision=0x0
Local APIC ADDR=0xfee00000
Flags={PC-AT}
Type=Local APIC
ACPI CPU=0
Flags={ENABLED}
APIC ID=0
Type=Local APIC
ACPI CPU=1
Flags={ENABLED}
APIC ID=1
Type=IO APIC
APIC ID=2
INT BASE=0
ADDR=0x00000000fec00000
Type=INT Override
BUS=0
IRQ=0
INTR=2
Flags={Polarity=conforming, Trigger=conforming}
Type=INT Override
BUS=0
IRQ=9
INTR=9
Flags={Polarity=active-lo, Trigger=level}
Type=Local APIC NMI
ACPI CPU=0
LINT Pin=1
Flags={Polarity=active-hi, Trigger=edge}
Type=Local APIC NMI
ACPI CPU=1
LINT Pin=1
Flags={Polarity=active-hi, Trigger=edge}
*/
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20100528
*
* Disassembly of /tmp/acpidump.03702a, Sat Aug 14 16:13:38 2010
*
*
* Original Table Header:
* Signature "DSDT"
* Length 0x00004D8C (19852)
* Revision 0x01 **** ACPI 1.0, no 64-bit math support
* Checksum 0xB3
* OEM ID "CN400 "
* OEM Table ID "AWRDACPI"
* OEM Revision 0x00001000 (4096)
* Compiler ID "MSFT"
* Compiler Version 0x0100000E (16777230)
*/
DefinitionBlock ("/tmp/acpidump.aml", "DSDT", 1, "CN400 ", "AWRDACPI",
0x00001000)
{
Scope (\_PR)
{
Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) {}
Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00) {}
}
Name (\_S0, Package (0x04)
{
0x00,
0x00,
0x00,
0x00
})
Name (\SS1, Package (0x04)
{
0x04,
0x04,
0x04,
0x04
})
Name (\_S3, Package (0x04)
{
0x01,
0x01,
0x01,
0x01
})
Name (\_S4, Package (0x04)
{
0x02,
0x02,
0x02,
0x02
})
Name (\_S5, Package (0x04)
{
0x02,
0x02,
0x02,
0x02
})
OperationRegion (\DEBG, SystemIO, 0x80, 0x01)
Field (\DEBG, ByteAcc, NoLock, Preserve)
{
DBG1, 8
}
OperationRegion (\DEB2, SystemIO, 0x84, 0x01)
Field (\DEB2, ByteAcc, NoLock, Preserve)
{
DBG2, 8
}
OperationRegion (\DEB3, SystemIO, 0x88, 0x01)
Field (\DEB3, ByteAcc, NoLock, Preserve)
{
DBG3, 8
}
OperationRegion (EXTM, SystemMemory, 0x000FF830, 0x10)
Field (EXTM, WordAcc, NoLock, Preserve)
{
ROM1, 16,
RMS1, 16,
ROM2, 16,
RMS2, 16,
ROM3, 16,
RMS3, 16,
AMEM, 32
}
OperationRegion (\GPST, SystemIO, 0x0420, 0x02)
Field (\GPST, ByteAcc, NoLock, Preserve)
{
GS00, 1,
GS01, 1,
GS02, 1,
GS03, 1,
GS04, 1,
GS05, 1,
GS06, 1,
GS07, 1,
GS08, 1,
GS09, 1,
GS10, 1,
GS11, 1,
GS12, 1,
GS13, 1,
GS14, 1,
GS15, 1
}
OperationRegion (ELCR, SystemIO, 0x04D0, 0x02)
Field (ELCR, ByteAcc, NoLock, Preserve)
{
ELC1, 8,
ELC2, 8
}
OperationRegion (\PMS, SystemIO, 0x0400, 0x02)
Field (\PMS, ByteAcc, NoLock, Preserve)
{
AITS, 1,
Offset (0x01),
PBTS, 1,
, 6,
WAKE, 1
}
OperationRegion (\GPSE, SystemIO, 0x0424, 0x02)
Field (\GPSE, ByteAcc, NoLock, Preserve)
{
GPS0, 1,
GPS1, 1,
KBCE, 1,
LANE, 1,
EXTE, 1,
PME, 1,
Offset (0x01),
RING, 1,
, 5,
USBE, 1,
Offset (0x02)
}
OperationRegion (\GLOS, SystemIO, 0x0428, 0x02)
Field (\GLOS, ByteAcc, NoLock, Preserve)
{
, 6,
SSMI, 1,
PRII, 1,
, 2,
SLPE, 1,
SIRS, 1,
Offset (0x02)
}
OperationRegion (\WIRQ, SystemIO, 0x042A, 0x01)
Field (\WIRQ, ByteAcc, NoLock, Preserve)
{
IRQR, 8
}
OperationRegion (\SMIC, SystemIO, 0x042F, 0x01)
Field (\SMIC, ByteAcc, NoLock, Preserve)
{
SCP, 8
}
OperationRegion (\STUS, SystemIO, 0x0430, 0x01)
Field (\STUS, ByteAcc, NoLock, Preserve)
{
, 1,
PADS, 7
}
OperationRegion (GPOB, SystemIO, 0x044C, 0x04)
Field (GPOB, ByteAcc, NoLock, Preserve)
{
GP00, 1,
GP01, 1,
GP02, 1,
GP03, 1,
GP04, 1,
GP05, 1,
GP06, 1,
GP07, 1,
GP08, 1,
GP09, 1,
GP10, 1,
GP11, 1,
GP12, 1,
GP13, 1,
GP14, 1,
GP15, 1,
GP16, 1,
GP17, 1,
GP18, 1,
GP19, 1,
GP20, 1,
GP21, 1,
GP22, 1,
GP23, 1,
GP24, 1,
GP25, 1,
GP26, 1,
GP27, 1,
GP28, 1,
GP29, 1,
GP30, 1,
GPXX, 1
}
Name (OSFX, 0x01)
Name (OSFL, 0x01)
Method (STRC, 2, NotSerialized)
{
If (LNotEqual (SizeOf (Arg0), SizeOf (Arg1)))
{
Return (0x00)
}
Add (SizeOf (Arg0), 0x01, Local0)
Name (BUF0, Buffer (Local0) {})
Name (BUF1, Buffer (Local0) {})
Store (Arg0, BUF0)
Store (Arg1, BUF1)
While (Local0)
{
Decrement (Local0)
If (LNotEqual (DerefOf (Index (BUF0, Local0)), DerefOf (Index (
BUF1, Local0))))
{
Return (Zero)
}
}
Return (One)
}
OperationRegion (RTCM, SystemIO, 0x70, 0x02)
Field (RTCM, ByteAcc, NoLock, Preserve)
{
CMIN, 8,
CMDA, 8
}
IndexField (CMIN, CMDA, ByteAcc, NoLock, Preserve)
{
Offset (0x0F),
SHUT, 8
}
OperationRegion (INFO, SystemMemory, 0x000FF840, 0x01)
Field (INFO, ByteAcc, NoLock, Preserve)
{
KBDI, 1,
RTCW, 1,
PS2F, 1,
IRFL, 2,
DISE, 1,
SSHU, 1
}
OperationRegion (BEEP, SystemIO, 0x61, 0x01)
Field (BEEP, ByteAcc, NoLock, Preserve)
{
S1B, 8
}
OperationRegion (CONT, SystemIO, 0x40, 0x04)
Field (CONT, ByteAcc, NoLock, Preserve)
{
CNT0, 8,
CNT1, 8,
CNT2, 8,
CTRL, 8
}
Method (SPKR, 1, NotSerialized)
{
Store (S1B, Local0)
Store (0xB6, CTRL)
Store (0x55, CNT2)
Store (0x03, CNT2)
Store (Arg0, Local2)
While (LGreater (Local2, 0x00))
{
Or (S1B, 0x03, S1B)
Store (0x5FFF, Local3)
While (LGreater (Local3, 0x00))
{
Decrement (Local3)
}
And (S1B, 0xFC, S1B)
Store (0x0EFF, Local3)
While (LGreater (Local3, 0x00))
{
Decrement (Local3)
}
Decrement (Local2)
}
Store (Local0, S1B)
}
Scope (\)
{
Name (PICF, 0x00)
Method (_PIC, 1, NotSerialized)
{
Store (Arg0, PICF)
}
}
Name (SBFL, 0x00)
Name (ATFL, 0x00)
Method (\_PTS, 1, NotSerialized)
{
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG1)
OSTP ()
If (LEqual (Arg0, 0x01))
{
While (PRII)
{
Store (One, PRII)
}
While (LNotEqual (PADS, 0x00))
{
Store (PADS, PADS)
}
Or (IRQR, 0x80, IRQR)
}
If (LEqual (Arg0, 0x03))
{
Or (Arg0, 0x50, Local1)
Store (Local1, SCP)
}
If (LEqual (Arg0, 0x04))
{
Store (One, LANE)
}
If (LEqual (Arg0, 0x05))
{
Store (One, LANE)
}
Sleep (0x64)
If (LEqual (Arg0, 0x01)) {}
If (LEqual (Arg0, 0x03)) {}
If (LEqual (Arg0, 0x04)) {}
If (LEqual (Arg0, 0x05)) {}
}
Method (\_WAK, 1, NotSerialized)
{
Store (0xFF, DBG1)
If (LEqual (Arg0, 0x01)) {}
If (LEqual (Arg0, 0x03)) {}
If (LEqual (Arg0, 0x01))
{
And (IRQR, 0x7F, IRQR)
While (PRII)
{
Store (One, PRII)
}
While (LNotEqual (PADS, 0x00))
{
Store (PADS, PADS)
}
}
If (OSFL)
{
Notify (\_SB.PWRB, 0x02)
}
Else
{
If (LEqual (RTCW, 0x00))
{
Notify (\_SB.PWRB, 0x02)
}
}
}
Scope (\_SI)
{
Method (_MSG, 1, NotSerialized)
{
Store (Local0, Local0)
}
Method (_SST, 1, NotSerialized)
{
If (LEqual (Arg0, 0x03)) {}
If (LEqual (Arg0, 0x01)) {}
If (LEqual (Arg0, Zero)) {}
Store (Local0, Local0)
}
}
OperationRegion (TEMM, SystemMemory, 0x000FF810, 0x0C)
Field (TEMM, WordAcc, NoLock, Preserve)
{
TP1H, 16,
TP1L, 16,
TP2H, 16,
TP2L, 16,
TRPC, 16,
SENF, 16
}
Name (TVAR, Buffer (0x05)
{
0x00, 0x00, 0x00, 0x00, 0x00
})
CreateByteField (TVAR, 0x00, PLCY)
CreateWordField (TVAR, 0x01, CTOS)
CreateWordField (TVAR, 0x03, CTHY)
Name (TBUF, Buffer (0x04)
{
0x00, 0x00, 0x00, 0x00
})
CreateByteField (TBUF, 0x00, DB00)
CreateByteField (TBUF, 0x01, DB01)
CreateWordField (TBUF, 0x00, DW00)
CreateWordField (TBUF, 0x02, DW01)
CreateDWordField (TBUF, 0x00, DATD)
OperationRegion (IP, SystemIO, 0x0295, 0x02)
Field (IP, ByteAcc, NoLock, Preserve)
{
INDS, 8,
DATS, 8
}
Method (SCFG, 1, NotSerialized)
{
SBYT (0x40, Arg0)
}
Method (STOS, 3, NotSerialized)
{
Store (GBYT (0x4E), Local0)
Or (Local0, 0x01, Local1)
SBYT (0x4E, Local1)
SBYT (0x55, Arg1)
SBYT (0x56, Arg0)
SBYT (0x4E, Local0)
}
Method (STHY, 3, NotSerialized)
{
Store (GBYT (0x4E), Local0)
Or (Local0, 0x01, Local1)
SBYT (0x4E, Local1)
SBYT (0x53, Arg1)
SBYT (0x54, Arg0)
SBYT (0x4E, Local0)
}
Method (RTMP, 0, NotSerialized)
{
Store (GBYT (0x4E), Local0)
Or (Local0, 0x01, Local1)
SBYT (0x4E, Local1)
Store (GBYT (0x50), Local1)
Store (GBYT (0x51), Local2)
ShiftLeft (Local1, 0x08, Local1)
Or (Local1, Local2, Local3)
ShiftRight (Local3, 0x07, Local3)
ShiftLeft (Local3, 0x02, Local1)
Add (Local3, Local1, Local3)
Add (Local3, 0x0AAC, Local3)
If (LGreater (Local3, 0x0E8A))
{
Store (0x0AAC, Local3)
}
SBYT (0x4E, Local0)
Return (Local3)
}
Method (SBYT, 2, NotSerialized)
{
Store (Arg0, INDS)
Store (Arg1, DATS)
}
Method (GBYT, 1, NotSerialized)
{
Store (Arg0, INDS)
Store (DATS, Local7)
Return (Local7)
}
Scope (\_TZ)
{
Device (FAN)
{
Name (_HID, EisaId ("PNP0C0B"))
Method (_INI, 0, NotSerialized)
{
Store (TP1H, CTOS)
Store (TP1L, CTHY)
}
}
ThermalZone (THRM)
{
Name (_AL0, Package (0x01)
{
FAN
})
Method (_AC0, 0, NotSerialized)
{
If (Or (PLCY, PLCY, Local7))
{
Return (TP2H)
}
Else
{
Return (TP1H)
}
}
Name (_PSL, Package (0x01)
{
\_PR.CPU0
})
Name (_TSP, 0x3C)
Name (_TC1, 0x04)
Name (_TC2, 0x03)
Method (_PSV, 0, NotSerialized)
{
If (Or (PLCY, PLCY, Local7))
{
Return (TP1H)
}
Else
{
Return (TP2H)
}
}
Method (_CRT, 0, NotSerialized)
{
Return (TRPC)
}
Method (_TMP, 0, NotSerialized)
{
And (SENF, 0x01, Local6)
If (LEqual (Local6, 0x01))
{
Return (RTMP ())
}
Else
{
Return (0x0B86)
}
}
Method (_SCP, 1, NotSerialized)
{
If (Arg0)
{
Store (One, PLCY)
}
Else
{
Store (Zero, PLCY)
}
Notify (\_TZ.THRM, 0x81)
}
Method (STMP, 2, NotSerialized)
{
Store (Arg1, DW00)
If (Arg0)
{
STHY (DB00, DB01, DW00)
}
Else
{
STOS (DB00, DB01, DW00)
}
}
}
}
Scope (\_GPE)
{
Method (_L03, 0, NotSerialized)
{
Notify (\_SB.PCI0.LAN0, 0x02)
}
Method (_L09, 0, NotSerialized)
{
If (LEqual (SBFL, 0x00))
{
Notify (\_SB.PCI0.USB0, 0x02)
Notify (\_SB.PCI0.USB1, 0x02)
Notify (\_SB.PCI0.USB2, 0x02)
}
If (LEqual (SBFL, 0x01))
{
Notify (\_SB.PCI0.USB0, 0x02)
Notify (\_SB.PCI0.USB1, 0x02)
}
}
Method (_L0E, 0, NotSerialized)
{
If (LEqual (SBFL, 0x02))
{
Notify (\_SB.PCI0.USB3, 0x02)
Notify (\_SB.PCI0.USB4, 0x02)
Notify (\_SB.PCI0.USB5, 0x02)
Notify (\_SB.PCI0.USB6, 0x02)
}
If (LEqual (SBFL, 0x03))
{
Notify (\_SB.PCI0.USB3, 0x02)
Notify (\_SB.PCI0.USB4, 0x02)
Notify (\_SB.PCI0.USB5, 0x02)
Notify (\_SB.PCI0.USB6, 0x02)
Notify (\_SB.PCI0.USB7, 0x02)
}
}
Method (_L0A, 0, NotSerialized)
{
Notify (\_TZ.THRM, 0x80)
}
Method (_L05, 0, NotSerialized)
{
Notify (\_SB.PCI0, 0x02)
}
Method (_L08, 0, NotSerialized)
{
Notify (\_SB.PCI0.UAR1, 0x02)
}
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.AC97, 0x02)
}
}
Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
Method (_STA, 0, NotSerialized)
{
Return (0x0B)
}
}
Device (MEM)
{
Name (_HID, EisaId ("PNP0C01"))
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0x000F0000, // Address Base
0x00004000, // Address Length
_Y01)
Memory32Fixed (ReadWrite,
0x000F4000, // Address Base
0x00004000, // Address Length
_Y02)
Memory32Fixed (ReadWrite,
0x000F8000, // Address Base
0x00004000, // Address Length
_Y03)
Memory32Fixed (ReadWrite,
0x000FC000, // Address Base
0x00004000, // Address Length
_Y04)
Memory32Fixed (ReadWrite,
0x00000000, // Address Base
0x00010000, // Address Length
_Y00)
Memory32Fixed (ReadWrite,
0xFFFF0000, // Address Base
0x00010000, // Address Length
)
Memory32Fixed (ReadWrite,
0x00000000, // Address Base
0x000A0000, // Address Length
)
Memory32Fixed (ReadWrite,
0x00100000, // Address Base
0x00000000, // Address Length
_Y05)
Memory32Fixed (ReadWrite,
0xFEC00000, // Address Base
0x00001000, // Address Length
)
Memory32Fixed (ReadWrite,
0xFEE00000, // Address Base
0x00001000, // Address Length
)
Memory32Fixed (ReadWrite,
0xFFF80000, // Address Base
0x00070000, // Address Length
)
})
CreateDWordField (BUF0, \_SB.MEM._CRS._Y00._BAS, ACMM)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y00._LEN, ASSM)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y01._BAS, RMA1)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y01._LEN, RSS1)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y02._BAS, RMA2)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y02._LEN, RSS2)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y03._BAS, RMA3)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y03._LEN, RSS3)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y04._BAS, RMA4)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y04._LEN, RSS4)
CreateDWordField (BUF0, \_SB.MEM._CRS._Y05._LEN, EXTM)
Subtract (AMEM, 0x00100000, EXTM)
If (LNotEqual (ROM1, Zero))
{
Store (RMA1, RMA2)
ShiftLeft (ROM1, 0x08, Local0)
Store (Local0, RMA1)
ShiftLeft (RMS1, 0x08, Local0)
Store (Local0, RSS1)
Store (0x8000, RSS2)
}
If (LNotEqual (ROM2, Zero))
{
Store (RMA2, RMA3)
ShiftLeft (ROM2, 0x08, Local0)
Store (Local0, RMA2)
ShiftLeft (RMS2, 0x08, Local0)
Store (Local0, RSS2)
Store (0xC000, RSS3)
}
If (LNotEqual (ROM3, Zero))
{
Store (RMA3, RMA4)
ShiftLeft (ROM3, 0x08, Local0)
Store (Local0, RMA3)
ShiftLeft (RMS3, 0x08, Local0)
Store (Local0, RSS3)
Store (0x00010000, RSS4)
}
Store (AMEM, ACMM)
And (AMEM, 0x000FFFFF, Local0)
Subtract (0x00100000, Local0, ASSM)
Return (BUF0)
}
}
Device (PCI0)
{
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
Name (_UID, 0x01)
Name (_BBN, 0x00)
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (GART, PCI_Config, 0x80, 0x01)
Scope (\)
{
Field (\_SB.PCI0.GART, ByteAcc, NoLock, Preserve)
{
GAR1, 8
}
}
OperationRegion (GARA, PCI_Config, 0x88, 0x01)
Scope (\)
{
Field (\_SB.PCI0.GARA, ByteAcc, NoLock, Preserve)
{
GAR2, 8
}
}
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Name (_PRW, Package (0x02)
{
0x05,
0x05
})
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
WordBusNumber (ResourceConsumer, MinNotFixed,
MaxNotFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
IO (Decode16,
0x0CF8, // Range Minimum
0x0CF8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
WordIO (ResourceProducer, MinFixed, MaxFixed,
PosDecode, EntireRange,
0x0000, // Granularity
0x0000, // Range Minimum
0x0CF7, // Range Maximum
0x0000, // Translation Offset
0x0CF8, // Length
,, , TypeStatic)
WordIO (ResourceProducer, MinFixed, MaxFixed,
PosDecode, EntireRange,
0x0000, // Granularity
0x0D00, // Range Minimum
0xFFFF, // Range Maximum
0x0000, // Translation Offset
0xF300, // Length
,, , TypeStatic)
DWordMemory (ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Granularity
0x000A0000, // Range Minimum
0x000BFFFF, // Range Maximum
0x00000000, // Translation Offset
0x00020000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordMemory (ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Granularity
0x000C0000, // Range Minimum
0x000DFFFF, // Range Maximum
0x00000000, // Translation Offset
0x00020000, // Length
,, , AddressRangeMemory, TypeStatic)
DWordMemory (ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Granularity
0x00100000, // Range Minimum
0xFEBFFFFF, // Range Maximum
0x00000000, // Translation Offset
0xFFF00000, // Length
,, _Y06, AddressRangeMemory, TypeStatic)
})
CreateDWordField (BUF0, \_SB.PCI0._CRS._Y06._MIN, TCMM)
CreateDWordField (BUF0, \_SB.PCI0._CRS._Y06._LEN, TOMM)
Add (AMEM, 0x00010000, TCMM)
Add (TCMM, 0x00010000, TCMM)
Subtract (0xFEC00000, TCMM, TOMM)
Return (BUF0)
}
Name (PICM, Package (0x24)
{
Package (0x04)
{
0x0008FFFF,
0x00,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x0008FFFF,
0x01,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x0008FFFF,
0x02,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x0008FFFF,
0x03,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x0009FFFF,
0x00,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x0009FFFF,
0x01,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x0009FFFF,
0x02,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x0009FFFF,
0x03,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x000AFFFF,
0x00,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x000AFFFF,
0x01,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x000AFFFF,
0x02,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x000AFFFF,
0x03,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x000BFFFF,
0x00,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x000BFFFF,
0x01,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x000BFFFF,
0x02,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x000BFFFF,
0x03,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x0010FFFF,
0x00,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x0010FFFF,
0x01,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x0010FFFF,
0x02,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x0010FFFF,
0x03,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x00,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x01,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x02,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x03,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x0001FFFF,
0x00,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x0001FFFF,
0x01,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x0001FFFF,
0x02,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x0001FFFF,
0x03,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x0012FFFF,
0x00,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x0012FFFF,
0x01,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x0012FFFF,
0x02,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x0012FFFF,
0x03,
\_SB.PCI0.LNKD,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x00,
\_SB.PCI0.LNKA,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x01,
\_SB.PCI0.LNKB,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x02,
\_SB.PCI0.LNKC,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x03,
\_SB.PCI0.LNKD,
0x00
}
})
Name (APIC, Package (0x24)
{
Package (0x04)
{
0x0008FFFF,
0x00,
0x00,
0x10
},
Package (0x04)
{
0x0008FFFF,
0x01,
0x00,
0x11
},
Package (0x04)
{
0x0008FFFF,
0x02,
0x00,
0x12
},
Package (0x04)
{
0x0008FFFF,
0x03,
0x00,
0x13
},
Package (0x04)
{
0x0009FFFF,
0x00,
0x00,
0x11
},
Package (0x04)
{
0x0009FFFF,
0x01,
0x00,
0x12
},
Package (0x04)
{
0x0009FFFF,
0x02,
0x00,
0x13
},
Package (0x04)
{
0x0009FFFF,
0x03,
0x00,
0x10
},
Package (0x04)
{
0x000AFFFF,
0x00,
0x00,
0x12
},
Package (0x04)
{
0x000AFFFF,
0x01,
0x00,
0x13
},
Package (0x04)
{
0x000AFFFF,
0x02,
0x00,
0x10
},
Package (0x04)
{
0x000AFFFF,
0x03,
0x00,
0x11
},
Package (0x04)
{
0x000BFFFF,
0x00,
0x00,
0x13
},
Package (0x04)
{
0x000BFFFF,
0x01,
0x00,
0x10
},
Package (0x04)
{
0x000BFFFF,
0x02,
0x00,
0x11
},
Package (0x04)
{
0x000BFFFF,
0x03,
0x00,
0x12
},
Package (0x04)
{
0x0010FFFF,
0x00,
ALKB,
0x00
},
Package (0x04)
{
0x0010FFFF,
0x01,
ALKB,
0x00
},
Package (0x04)
{
0x0010FFFF,
0x02,
ALKB,
0x00
},
Package (0x04)
{
0x0010FFFF,
0x03,
ALKB,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x00,
ALKA,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x01,
ALKB,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x02,
ALKC,
0x00
},
Package (0x04)
{
0x0011FFFF,
0x03,
ALKD,
0x00
},
Package (0x04)
{
0x0001FFFF,
0x00,
0x00,
0x10
},
Package (0x04)
{
0x0001FFFF,
0x01,
0x00,
0x11
},
Package (0x04)
{
0x0001FFFF,
0x02,
0x00,
0x12
},
Package (0x04)
{
0x0001FFFF,
0x03,
0x00,
0x13
},
Package (0x04)
{
0x0012FFFF,
0x00,
ALKD,
0x00
},
Package (0x04)
{
0x0012FFFF,
0x01,
ALKD,
0x00
},
Package (0x04)
{
0x0012FFFF,
0x02,
ALKD,
0x00
},
Package (0x04)
{
0x0012FFFF,
0x03,
ALKD,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x00,
ALKA,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x01,
ALKA,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x02,
ALKA,
0x00
},
Package (0x04)
{
0x000FFFFF,
0x03,
ALKA,
0x00
}
})
Method (_PRT, 0, NotSerialized)
{
If (LNot (PICF))
{
Return (PICM)
}
Else
{
Return (APIC)
}
}
Device (PMIO)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x02)
Method (_CRS, 0, NotSerialized)
{
Name (BUF0, ResourceTemplate ()
{
IO (Decode16,
0x0400, // Range Minimum
0x0400, // Range Maximum
0x01, // Alignment
0x80, // Length
)
IO (Decode16,
0x0500, // Range Minimum
0x0500, // Range Maximum
0x01, // Alignment
0x10, // Length
)
})
Return (BUF0)
}
}
Device (VT86)
{
Name (_ADR, 0x00110000)
OperationRegion (USBC, PCI_Config, 0x50, 0x02)
Scope (\)
{
Field (\_SB.PCI0.VT86.USBC, ByteAcc, NoLock, Preserve)
{
IDEB, 8
}
}
OperationRegion (VTSB, PCI_Config, 0x00, 0xE8)
Scope (\)
{
Field (\_SB.PCI0.VT86.VTSB, ByteAcc, NoLock, Preserve)
{
Offset (0x02),
DEID, 16,
Offset (0x2C),
ID2C, 8,
ID2D, 8,
ID2E, 8,
ID2F, 8,
Offset (0x44),
PIRE, 4,
PIRF, 4,
PIRG, 4,
PIRH, 4,
POLE, 1,
POLF, 1,
POLG, 1,
POLH, 1,
ENR8, 1,
Offset (0x50),
ESB4, 1,
ESB3, 1,
ESB2, 1,
EIDE, 1,
EUSB, 1,
ESB1, 1,
EAMC, 2,
EKBC, 1,
KBCC, 1,
EPS2, 1,
ERTC, 1,
ELAN, 1,
, 2,
USBD, 1,
SIRQ, 8,
Offset (0x55),
PIRA, 8,
PIBC, 8,
PIRD, 8,
Offset (0x75),
BSAT, 1,
Offset (0x94),
PWC1, 2,
GPO1, 1,
GPO2, 1,
GPO3, 1,
PLLD, 1
}
}
Scope (\)
{
Method (DISD, 1, NotSerialized)
{
Store (Local0, Local0)
}
Method (CKIO, 2, NotSerialized)
{
Store (Local0, Local0)
}
Method (SLDM, 2, NotSerialized)
{
Store (Local0, Local0)
}
}
}
Device (IDE0)
{
Name (_ADR, 0x00110001)
Name (REGF, 0x01)
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (CMD0, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
Method (_REG, 2, NotSerialized)
{
If (LEqual (Arg0, 0x02))
{
Store (Arg1, REGF)
}
}
OperationRegion (VIDE, PCI_Config, 0x00, 0xC2)
Scope (\)
{
Field (\_SB.PCI0.IDE0.VIDE, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMD0, 3,
Offset (0x09),
ENAT, 4,
Offset (0x3C),
IDEI, 8
}
}
Method (A133, 0, NotSerialized)
{
If (LNotEqual (DEID, 0x3177))
{
If (LEqual (DEID, 0x3147))
{
Return (One)
}
Else
{
Return (Zero)
}
}
Else
{
Return (One)
}
}
Name (TIM0, Package (0x0F)
{
Package (0x04)
{
0x78,
0xB4,
0xF0,
0x0258
},
Package (0x04)
{
0x20,
0x31,
0x65,
0xA8
},
Package (0x08)
{
0x02,
0x01,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
},
Package (0x08)
{
0x04,
0x03,
0x02,
0x02,
0x01,
0x01,
0x00,
0x00
},
Package (0x06)
{
0x78,
0x50,
0x3C,
0x2D,
0x1E,
0x14
},
Package (0x05)
{
0x02,
0x01,
0x00,
0x00,
0x00
},
Package (0x05)
{
0x06,
0x04,
0x02,
0x01,
0x00
},
Package (0x05)
{
0x00,
0x00,
0x00,
0x01,
0x01
},
Package (0x04)
{
0x04,
0x03,
0x02,
0x00
},
Package (0x04)
{
0x02,
0x01,
0x00,
0x00
},
Package (0x0B)
{
0x05,
0x04,
0x03,
0x03,
0x02,
0x02,
0x01,
0x01,
0x01,
0x01,
0x00
},
Package (0x06)
{
0x0A,
0x06,
0x04,
0x02,
0x01,
0x00
},
Package (0x07)
{
0x78,
0x50,
0x3C,
0x2D,
0x1E,
0x14,
0x0F
},
Package (0x0F)
{
0x06,
0x05,
0x04,
0x04,
0x03,
0x03,
0x02,
0x02,
0x01,
0x01,
0x01,
0x01,
0x01,
0x01,
0x00
},
Package (0x07)
{
0x0E,
0x08,
0x06,
0x04,
0x02,
0x01,
0x00
}
})
Name (TMD0, Buffer (0x14) {})
CreateDWordField (TMD0, 0x00, PIO0)
CreateDWordField (TMD0, 0x04, DMA0)
CreateDWordField (TMD0, 0x08, PIO1)
CreateDWordField (TMD0, 0x0C, DMA1)
CreateDWordField (TMD0, 0x10, CHNF)
OperationRegion (CFG2, PCI_Config, 0x40, 0x20)
Field (CFG2, DWordAcc, NoLock, Preserve)
{
Offset (0x08),
SSPT, 8,
SMPT, 8,
PSPT, 8,
PMPT, 8,
Offset (0x10),
SSUT, 4,
SSCT, 1,
SSUE, 3,
SMUT, 4,
SMCT, 1,
SMUE, 3,
PSUT, 4,
PSCT, 1,
PSUE, 3,
PMUT, 4,
PMCT, 1,
PMUE, 3
}
Name (GMPT, 0x00)
Name (GMUE, 0x00)
Name (GMUT, 0x00)
Name (GSPT, 0x00)
Name (GSUE, 0x00)
Name (GSUT, 0x00)
Name (GBCS, 0x00)
Device (CHN0)
{
Name (_ADR, 0x00)
Method (_GTM, 0, NotSerialized)
{
Return (GTM (PMPT, PMUE, PMUT, PSPT, PSUE, PSUT))
}
Method (_STM, 3, NotSerialized)
{
Store (Arg0, TMD0)
Store (PMPT, GMPT)
Store (PMUE, GMUE)
Store (PMUT, GMUT)
Store (PSPT, GSPT)
Store (PSUE, GSUE)
Store (PSUT, GSUT)
STM ()
Store (GMPT, PMPT)
Store (GMUE, PMUE)
Store (GMUT, PMUT)
Store (GSPT, PSPT)
Store (GSUE, PSUE)
Store (GSUT, PSUT)
}
Device (DRV0)
{
Name (_ADR, 0x00)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x00, PMUE, PMUT, PMPT))
}
}
Device (DRV1)
{
Name (_ADR, 0x01)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x01, PSUE, PSUT, PSPT))
}
}
}
Device (CHN1)
{
Name (_ADR, 0x01)
Method (_GTM, 0, NotSerialized)
{
Return (GTM (SMPT, SMUE, SMUT, SSPT, SSUE, SSUT))
}
Method (_STM, 3, NotSerialized)
{
Store (Arg0, TMD0)
Store (SMPT, GMPT)
Store (SMUE, GMUE)
Store (SMUT, GMUT)
Store (SSPT, GSPT)
Store (SSUE, GSUE)
Store (SSUT, GSUT)
STM ()
Store (GMPT, SMPT)
Store (GMUE, SMUE)
Store (GMUT, SMUT)
Store (GSPT, SSPT)
Store (GSUE, SSUE)
Store (GSUT, SSUT)
}
Device (DRV0)
{
Name (_ADR, 0x00)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x02, SMUE, SMUT, SMPT))
}
}
Device (DRV1)
{
Name (_ADR, 0x01)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x03, SSUE, SSUT, SSPT))
}
}
}
Method (GTF, 4, Serialized)
{
Store (Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
}, Local1)
Store (Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
}, Local2)
CreateByteField (Local1, 0x01, MODE)
CreateByteField (Local2, 0x01, UMOD)
CreateByteField (Local1, 0x05, PCHA)
CreateByteField (Local2, 0x05, UCHA)
And (Arg0, 0x03, Local3)
If (LEqual (And (Local3, 0x01), 0x01))
{
Store (0xB0, PCHA)
Store (0xB0, UCHA)
}
If (Arg1)
{
If (A133 ())
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0D)), Arg2)),
UMOD)
}
Else
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0A)), Arg2)),
UMOD)
}
Or (UMOD, 0x40, UMOD)
}
Else
{
Store (Match (DerefOf (Index (TIM0, 0x01)),
MEQ, Arg3, MTR,
0x00, 0x00), Local0)
Or (0x20, DerefOf (Index (DerefOf (Index
(TIM0, 0x09)), Local0
)), UMOD)
}
Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
0x00, 0x00), Local0)
Or (0x08, DerefOf (Index (DerefOf (Index (TIM0,
0x08)), Local0
)), MODE)
Concatenate (Local1, Local2, Local6)
Return (Local6)
}
Method (GTM, 6, Serialized)
{
Store (Ones, PIO0)
Store (Ones, PIO1)
Store (Ones, DMA0)
Store (Ones, DMA1)
Store (0x10, CHNF)
If (REGF) {}
Else
{
Return (TMD0)
}
Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg0, MTR,
0x00, 0x00), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x00)), Local6)),
Local7)
Store (Local7, DMA0)
Store (Local7, PIO0)
Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
0x00, 0x00), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x00)), Local6)),
Local7)
Store (Local7, DMA1)
Store (Local7, PIO1)
If (Arg1)
{
If (A133 ())
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0D)), Arg2)),
Local5)
}
Else
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0A)), Arg2)),
Local5)
}
If (A133 ())
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0C)), Local5)),
DMA0)
}
Else
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x04)), Local5)),
DMA0)
}
Or (CHNF, 0x01, CHNF)
}
If (Arg4)
{
If (A133 ())
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0D)), Arg5)),
Local5)
}
Else
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0A)), Arg5)),
Local5)
}
If (A133 ())
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0C)), Local5)),
DMA1)
}
Else
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x04)), Local5)),
DMA1)
}
Or (CHNF, 0x04, CHNF)
}
Return (TMD0)
}
Method (STM, 0, Serialized)
{
If (REGF) {}
Else
{
Return (TMD0)
}
Store (0x00, GMUE)
Store (0x00, GSUE)
Store (0x07, GMUT)
Store (0x07, GSUT)
If (And (CHNF, 0x01))
{
If (A133 ())
{
Store (Match (DerefOf (Index (TIM0,
0x0C)), MLE, DMA0, MTR,
0x00, 0x00), Local0)
}
Else
{
Store (Match (DerefOf (Index (TIM0,
0x04)), MLE, DMA0, MTR,
0x00, 0x00), Local0)
}
If (A133 ())
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0E)), Local0)),
GMUT)
}
Else
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0B)), Local0)),
GMUT)
}
Or (GMUE, 0x07, GMUE)
}
Else
{
If (Or (LEqual (PIO0, Ones), LEqual (PIO0, 0x00)))
{
If (And (LLess (DMA0, Ones), LGreater (DMA0, 0x00)))
{
Store (DMA0, PIO0)
}
}
}
If (And (CHNF, 0x04))
{
If (A133 ())
{
Store (Match (DerefOf (Index (TIM0,
0x0C)), MLE, DMA1, MTR,
0x00, 0x00), Local0)
}
Else
{
Store (Match (DerefOf (Index (TIM0,
0x04)), MLE, DMA1, MTR,
0x00, 0x00), Local0)
}
If (A133 ())
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0E)), Local0)),
GSUT)
}
Else
{
Store (DerefOf (Index (DerefOf (Index
(TIM0, 0x0B)), Local0)),
GSUT)
}
Or (GSUE, 0x07, GSUE)
}
Else
{
If (Or (LEqual (PIO1, Ones), LEqual (PIO1, 0x00)))
{
If (And (LLess (DMA1, Ones), LGreater (DMA1, 0x00)))
{
Store (DMA1, PIO1)
}
}
}
And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO0, MTR,
0x00, 0x00), 0x03, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x01)), Local0)),
Local1)
Store (Local1, GMPT)
And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR,
0x00, 0x00), 0x03, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x01)), Local0)),
Local1)
Store (Local1, GSPT)
}
}
Device (SATA)
{
Name (_ADR, 0x000F0000)
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.SATA.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
OperationRegion (SAPR, PCI_Config, 0x00, 0xC2)
Field (SAPR, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
IDEI, 8,
Offset (0x49),
, 6,
EPHY, 1
}
}
Device (PATA)
{
Name (_ADR, 0x000F0001)
Name (REGF, 0x01)
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
{
Return (0x00)
}
Else
{
PMEX ()
If (LEqual (\_SB.PCI0.PATA.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
Method (_REG, 2, NotSerialized)
{
If (LEqual (Arg0, 0x02))
{
Store (Arg1, REGF)
}
}
Name (TIM0, Package (0x07)
{
Package (0x05)
{
0x78,
0xB4,
0xF0,
0x017F,
0x0258
},
Package (0x05)
{
0x20,
0x22,
0x33,
0x47,
0x5D
},
Package (0x05)
{
0x04,
0x03,
0x02,
0x01,
0x00
},
Package (0x04)
{
0x02,
0x01,
0x00,
0x00
},
Package (0x07)
{
0x78,
0x50,
0x3C,
0x2D,
0x1E,
0x14,
0x0F
},
Package (0x0F)
{
0x06,
0x05,
0x04,
0x04,
0x03,
0x03,
0x02,
0x02,
0x01,
0x01,
0x01,
0x01,
0x01,
0x01,
0x00
},
Package (0x07)
{
0x0E,
0x08,
0x06,
0x04,
0x02,
0x01,
0x00
}
})
Name (TMD0, Buffer (0x14) {})
CreateDWordField (TMD0, 0x00, PIO0)
CreateDWordField (TMD0, 0x04, DMA0)
CreateDWordField (TMD0, 0x08, PIO1)
CreateDWordField (TMD0, 0x0C, DMA1)
CreateDWordField (TMD0, 0x10, CHNF)
OperationRegion (PAPR, PCI_Config, 0x00, 0xC2)
Field (PAPR, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x09),
ENAT, 4,
Offset (0x3C),
IDEI, 8,
Offset (0x40),
ESCH, 1,
EPCH, 1,
Offset (0x48),
SSPT, 8,
SMPT, 8,
PSPT, 8,
PMPT, 8,
Offset (0x50),
SSUT, 4,
SSCT, 1,
SSUE, 3,
SMUT, 4,
SMCT, 1,
SMUE, 3,
PSUT, 4,
PSCT, 1,
PSUE, 3,
PMUT, 4,
PMCT, 1,
PMUE, 3
}
Name (GMPT, 0x00)
Name (GMUE, 0x00)
Name (GMUT, 0x00)
Name (GSPT, 0x00)
Name (GSUE, 0x00)
Name (GSUT, 0x00)
Device (CHN0)
{
Name (_ADR, 0x00)
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.PATA.EPCH, 0x01))
{
Return (0x00)
}
Else
{
Return (0x0F)
}
}
Method (_GTM, 0, NotSerialized)
{
Return (GTM (PMPT, PMUE, PMUT, PSPT, PSUE, PSUT))
}
Method (_STM, 3, NotSerialized)
{
Store (Arg0, TMD0)
Store (PMPT, GMPT)
Store (PMUE, GMUE)
Store (PMUT, GMUT)
Store (PSPT, GSPT)
Store (PSUE, GSUE)
Store (PSUT, GSUT)
STM ()
Store (GMPT, PMPT)
Store (GMUE, PMUE)
Store (GMUT, PMUT)
Store (GSPT, PSPT)
Store (GSUE, PSUE)
Store (GSUT, PSUT)
}
Device (DRV0)
{
Name (_ADR, 0x00)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x00, PMUE, PMUT, PMPT))
}
}
Device (DRV1)
{
Name (_ADR, 0x01)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x01, PSUE, PSUT, PSPT))
}
}
}
Device (CHN1)
{
Name (_ADR, 0x01)
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (ATFL, 0x02))
{
If (LEqual (\_SB.PCI0.SATA.EPHY, 0x01))
{
Return (0x00)
}
Else
{
If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
{
Return (0x00)
}
Else
{
Return (0x0F)
}
}
}
If (LEqual (ATFL, 0x02))
{
If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
{
Return (0x00)
}
Else
{
Return (0x0F)
}
}
}
Method (_GTM, 0, NotSerialized)
{
Return (GTM (SMPT, SMUE, SMUT, SSPT, SSUE, SSUT))
}
Method (_STM, 3, NotSerialized)
{
Store (Arg0, TMD0)
Store (SMPT, GMPT)
Store (SMUE, GMUE)
Store (SMUT, GMUT)
Store (SSPT, GSPT)
Store (SSUE, GSUE)
Store (SSUT, GSUT)
STM ()
Store (GMPT, SMPT)
Store (GMUE, SMUE)
Store (GMUT, SMUT)
Store (GSPT, SSPT)
Store (GSUE, SSUE)
Store (GSUT, SSUT)
}
Device (DRV0)
{
Name (_ADR, 0x00)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x02, SMUE, SMUT, SMPT))
}
}
Device (DRV1)
{
Name (_ADR, 0x01)
Method (_GTF, 0, NotSerialized)
{
Return (GTF (0x03, SSUE, SSUT, SSPT))
}
}
}
Method (PMEX, 0, Serialized)
{
If (REGF)
{
If (LEqual (PMPT, 0xA8))
{
Store (0x5D, PMPT)
}
If (LEqual (PMPT, 0x65))
{
Store (0x33, PMPT)
}
If (LEqual (PMPT, 0x31))
{
Store (0x22, PMPT)
}
If (LEqual (PSPT, 0xA8))
{
Store (0x5D, PSPT)
}
If (LEqual (PSPT, 0x65))
{
Store (0x33, PSPT)
}
If (LEqual (PSPT, 0x31))
{
Store (0x22, PSPT)
}
If (LEqual (SMPT, 0xA8))
{
Store (0x5D, SMPT)
}
If (LEqual (SMPT, 0x65))
{
Store (0x33, SMPT)
}
If (LEqual (SMPT, 0x31))
{
Store (0x22, SMPT)
}
If (LEqual (SSPT, 0xA8))
{
Store (0x5D, SSPT)
}
If (LEqual (SSPT, 0x65))
{
Store (0x33, SSPT)
}
If (LEqual (SSPT, 0x31))
{
Store (0x22, SSPT)
}
}
}
Method (GTF, 4, Serialized)
{
Store (Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
}, Local1)
Store (Buffer (0x07)
{
0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
}, Local2)
CreateByteField (Local1, 0x01, MODE)
CreateByteField (Local2, 0x01, UMOD)
CreateByteField (Local1, 0x05, PCHA)
CreateByteField (Local2, 0x05, UCHA)
And (Arg0, 0x03, Local3)
If (LEqual (And (Local3, 0x01), 0x01))
{
Store (0xB0, PCHA)
Store (0xB0, UCHA)
}
If (Arg1)
{
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x05)), Arg2)),
UMOD)
Or (UMOD, 0x40, UMOD)
}
Else
{
Store (Match (DerefOf (Index (TIM0, 0x01)),
MEQ, Arg3, MTR,
0x00, 0x00), Local0)
Or (0x20, DerefOf (Index (DerefOf (Index
(TIM0, 0x03)), Local0
)), UMOD)
}
Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
0x00, 0x00), Local0)
Or (0x08, DerefOf (Index (DerefOf (Index (TIM0,
0x02)), Local0
)), MODE)
Concatenate (Local1, Local2, Local6)
Return (Local6)
}
Method (GTM, 6, Serialized)
{
Store (Ones, PIO0)
Store (Ones, PIO1)
Store (Ones, DMA0)
Store (Ones, DMA1)
Store (0x10, CHNF)
If (REGF) {}
Else
{
Return (TMD0)
}
Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg0, MTR,
0x00, 0x00), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x00)), Local6)),
Local7)
Store (Local7, DMA0)
Store (Local7, PIO0)
Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
0x00, 0x00), Local6)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x00)), Local6)),
Local7)
Store (Local7, DMA1)
Store (Local7, PIO1)
If (Arg1)
{
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x05)), Arg2)),
Local5)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x04)), Local5)),
DMA0)
Or (CHNF, 0x01, CHNF)
}
If (Arg4)
{
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x05)), Arg5)),
Local5)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x04)), Local5)),
DMA1)
Or (CHNF, 0x04, CHNF)
}
Return (TMD0)
}
Method (STM, 0, Serialized)
{
If (REGF) {}
Else
{
Return (TMD0)
}
Store (0x00, GMUE)
Store (0x00, GSUE)
Store (0x07, GMUT)
Store (0x07, GSUT)
If (And (CHNF, 0x01))
{
Store (Match (DerefOf (Index (TIM0, 0x04)),
MLE, DMA0, MTR,
0x00, 0x00), Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x06)), Local0)),
GMUT)
Or (GMUE, 0x07, GMUE)
}
Else
{
If (Or (LEqual (PIO0, Ones), LEqual (PIO0, 0x00)))
{
If (And (LLess (DMA0, Ones), LGreater (DMA0, 0x00)))
{
Store (DMA0, PIO0)
}
}
}
If (And (CHNF, 0x04))
{
Store (Match (DerefOf (Index (TIM0, 0x04)),
MLE, DMA1, MTR,
0x00, 0x00), Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x06)), Local0)),
GSUT)
Or (GSUE, 0x07, GSUE)
}
Else
{
If (Or (LEqual (PIO1, Ones), LEqual (PIO1, 0x00)))
{
If (And (LLess (DMA1, Ones), LGreater (DMA1, 0x00)))
{
Store (DMA1, PIO1)
}
}
}
And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO0, MTR,
0x00, 0x00), 0x03, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x01)), Local0)),
Local1)
Store (Local1, GMPT)
And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR,
0x00, 0x00), 0x03, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0,
0x01)), Local0)),
Local1)
Store (Local1, GSPT)
}
}
Device (USB0)
{
Name (_ADR, 0x00110002)
Name (_PRW, Package (0x02)
{
0x09,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (SB72, PCI_Config, 0x00, 0xC2)
Field (SB72, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U0IR, 4
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB0.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB0.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (USB1)
{
Name (_ADR, 0x00110003)
Name (_PRW, Package (0x02)
{
0x09,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (SB73, PCI_Config, 0x00, 0xC2)
Field (SB73, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U1IR, 4
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB1.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB1.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (USB2)
{
Name (_ADR, 0x00110004)
Name (_PRW, Package (0x02)
{
0x09,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (SB74, PCI_Config, 0x00, 0xC2)
Field (SB74, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U2IR, 4
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB2.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB2.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (USB3)
{
Name (_ADR, 0x00100000)
Name (_PRW, Package (0x02)
{
0x0E,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (U2F0, PCI_Config, 0x00, 0xC2)
Field (U2F0, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U3IR, 4,
Offset (0x84),
ECDX, 2
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB3.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB3.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (USB4)
{
Name (_ADR, 0x00100001)
Name (_PRW, Package (0x02)
{
0x0E,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (U2F1, PCI_Config, 0x00, 0xC2)
Field (U2F1, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U4IR, 4,
Offset (0x84),
ECDX, 2
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB4.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB4.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (USB5)
{
Name (_ADR, 0x00100002)
Name (_PRW, Package (0x02)
{
0x0E,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (U2F2, PCI_Config, 0x00, 0xC2)
Field (U2F2, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U5IR, 4,
Offset (0x84),
ECDX, 2
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB5.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB5.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (USB6)
{
Name (_ADR, 0x00100003)
Name (_PRW, Package (0x02)
{
0x0E,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (U2F3, PCI_Config, 0x00, 0xC2)
Field (U2F3, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U6IR, 4,
Offset (0x84),
ECDX, 2
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB6.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB6.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (USB7)
{
Name (_ADR, 0x00100004)
Name (_PRW, Package (0x02)
{
0x0E,
0x03
})
Method (_S3D, 0, NotSerialized)
{
If (LEqual (OSFL, 0x02))
{
Return (0x02)
}
Else
{
Return (0x03)
}
}
OperationRegion (U2F4, PCI_Config, 0x00, 0xC2)
Field (U2F4, ByteAcc, NoLock, Preserve)
{
VID, 16,
Offset (0x04),
CMDR, 3,
Offset (0x3C),
U7IR, 4,
Offset (0x84),
ECDX, 2
}
Method (_STA, 0, NotSerialized)
{
If (LNotEqual (\_SB.PCI0.USB7.VID, 0x1106))
{
Return (0x00)
}
Else
{
If (LEqual (\_SB.PCI0.USB7.CMDR, 0x00))
{
Return (0x0D)
}
Else
{
Return (0x0F)
}
}
}
}
Device (LAN0)
{
Name (_ADR, 0x00120000)
Name (_PRW, Package (0x02)
{
0x03,
0x05
})
}
Device (AC97)
{
Name (_ADR, 0x00110005)
Name (_PRW, Package (0x02)
{
0x0D,
0x05
})
}
Device (LNKA)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
And (PIRA, 0xF0, Local0)
If (LEqual (Local0, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFB)
}
Method (_DIS, 0, NotSerialized)
{
And (PIRA, 0x0F, PIRA)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFB, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y07)
{}
})
CreateByteField (BUFB, \_SB.PCI0.LNKA._CRS._Y07._INT, IRB1)
CreateByteField (BUFB, 0x02, IRB2)
Store (0x00, Local3)
Store (0x00, Local4)
And (PIRA, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNotEqual (Local1, 0x00))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRB1)
Store (Local4, IRB2)
}
Return (BUFB)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRB1)
CreateByteField (Arg0, 0x02, IRB2)
ShiftLeft (IRB2, 0x08, Local0)
Or (Local0, IRB1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (PIRA, 0x0F, PIRA)
ShiftLeft (Local1, 0x04, Local1)
Or (PIRA, Local1, PIRA)
}
}
Device (LNKB)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
And (PIBC, 0x0F, Local0)
If (LEqual (Local0, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFA)
}
Method (_DIS, 0, NotSerialized)
{
And (PIBC, 0xF0, PIBC)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFA, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y08)
{}
})
CreateByteField (BUFA, \_SB.PCI0.LNKB._CRS._Y08._INT, IRA1)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local3)
Store (0x00, Local4)
And (PIBC, 0x0F, Local1)
If (LNotEqual (Local1, 0x00))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRA1)
Store (Local4, IRA2)
}
Return (BUFA)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (PIBC, 0xF0, PIBC)
Or (PIBC, Local1, PIBC)
}
}
Device (LNKC)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x03)
Method (_STA, 0, NotSerialized)
{
And (PIBC, 0xF0, Local0)
If (LEqual (Local0, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFC)
}
Method (_DIS, 0, NotSerialized)
{
And (PIBC, 0x0F, PIBC)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFC, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y09)
{}
})
CreateByteField (BUFC, \_SB.PCI0.LNKC._CRS._Y09._INT, IRC1)
CreateByteField (BUFC, 0x02, IRC2)
Store (0x00, Local3)
Store (0x00, Local4)
And (PIBC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNotEqual (Local1, 0x00))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRC1)
Store (Local4, IRC2)
}
Return (BUFC)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRC1)
CreateByteField (Arg0, 0x02, IRC2)
ShiftLeft (IRC2, 0x08, Local0)
Or (Local0, IRC1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (PIBC, 0x0F, PIBC)
ShiftLeft (Local1, 0x04, Local1)
Or (PIBC, Local1, PIBC)
}
}
Device (LNKD)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x04)
Method (_STA, 0, NotSerialized)
{
And (PIRD, 0xF0, Local0)
If (LEqual (Local0, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFD, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFD)
}
Method (_DIS, 0, NotSerialized)
{
And (PIRD, 0x0F, PIRD)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFD, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y0A)
{}
})
CreateByteField (BUFD, \_SB.PCI0.LNKD._CRS._Y0A._INT, IRD1)
CreateByteField (BUFD, 0x02, IRD2)
Store (0x00, Local3)
Store (0x00, Local4)
And (PIRD, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNotEqual (Local1, 0x00))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRD1)
Store (Local4, IRD2)
}
Return (BUFD)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRD1)
CreateByteField (Arg0, 0x02, IRD2)
ShiftLeft (IRD2, 0x08, Local0)
Or (Local0, IRD1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (PIRD, 0x0F, PIRD)
ShiftLeft (Local1, 0x04, Local1)
Or (PIRD, Local1, PIRD)
}
}
Device (LNKE)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x05)
Method (_STA, 0, NotSerialized)
{
If (LEqual (PIRE, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFE, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFE)
}
Method (_DIS, 0, NotSerialized)
{
Store (Zero, PIRE)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFE, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y0B)
{}
})
CreateByteField (BUFE, \_SB.PCI0.LNKE._CRS._Y0B._INT, IRE1)
CreateByteField (BUFE, 0x02, IRE2)
Store (Zero, IRE1)
Store (Zero, IRE2)
Store (PIRE, Local0)
If (LGreater (Local0, 0x00))
{
If (LGreater (Local0, 0x07))
{
Subtract (Local0, 0x08, Local1)
ShiftLeft (One, Local1, IRE2)
}
Else
{
Store (Local0, Local1)
ShiftLeft (One, Local1, IRE1)
}
}
Return (BUFE)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRE1)
CreateByteField (Arg0, 0x02, IRE2)
If (LGreater (IRE2, Zero))
{
FindSetLeftBit (IRE2, Local0)
Decrement (Local0)
Add (Local0, 0x08, Local0)
}
Else
{
FindSetLeftBit (IRE1, Local0)
Decrement (Local0)
}
Store (One, ENR8)
Store (Zero, POLE)
Store (Local0, PIRE)
}
}
Device (LNKF)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x06)
Method (_STA, 0, NotSerialized)
{
If (LEqual (PIRF, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFF, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFF)
}
Method (_DIS, 0, NotSerialized)
{
Store (Zero, PIRF)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFF, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y0C)
{}
})
CreateByteField (BUFF, \_SB.PCI0.LNKF._CRS._Y0C._INT, IRF1)
CreateByteField (BUFF, 0x02, IRF2)
Store (Zero, IRF1)
Store (Zero, IRF2)
Store (PIRF, Local0)
If (LGreater (Local0, 0x00))
{
If (LGreater (Local0, 0x07))
{
Subtract (Local0, 0x08, Local1)
ShiftLeft (One, Local0, IRF2)
}
Else
{
Store (Local0, Local1)
ShiftLeft (One, Local1, IRF1)
}
}
Return (BUFF)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRF1)
CreateByteField (Arg0, 0x02, IRF2)
If (LGreater (IRF2, Zero))
{
FindSetLeftBit (IRF2, Local0)
Decrement (Local0)
Add (Local0, 0x08, Local0)
}
Else
{
FindSetLeftBit (IRF1, Local0)
Decrement (Local0)
}
Store (One, ENR8)
Store (Zero, POLF)
Store (Local0, PIRF)
}
}
Device (LNK0)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x07)
Method (_STA, 0, NotSerialized)
{
If (LEqual (PIRG, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFG, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFG)
}
Method (_DIS, 0, NotSerialized)
{
Store (Zero, PIRG)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFG, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y0D)
{}
})
CreateByteField (BUFG, \_SB.PCI0.LNK0._CRS._Y0D._INT, IRG1)
CreateByteField (BUFG, 0x02, IRG2)
Store (Zero, IRG1)
Store (Zero, IRG2)
Store (PIRG, Local0)
If (LGreater (Local0, 0x00))
{
If (LGreater (Local0, 0x07))
{
Subtract (Local0, 0x08, Local0)
ShiftLeft (One, Local0, IRG2)
}
Else
{
Store (0x01, Local1)
ShiftLeft (Local1, Local0, IRG1)
}
}
Return (BUFG)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRG1)
CreateByteField (Arg0, 0x02, IRG2)
If (LGreater (IRG2, Zero))
{
FindSetLeftBit (IRG2, Local0)
Decrement (Local0)
Add (Local0, 0x08, Local0)
}
Else
{
FindSetLeftBit (IRG1, Local0)
Decrement (Local0)
}
Store (One, ENR8)
Store (Zero, POLG)
Store (Local0, PIRG)
}
}
Device (LNK1)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x08)
Method (_STA, 0, NotSerialized)
{
If (LEqual (PIRH, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (BUFH, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{3,4,6,7,10,11,12}
})
Return (BUFH)
}
Method (_DIS, 0, NotSerialized)
{
Store (Zero, PIRH)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUFH, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y0E)
{}
})
CreateByteField (BUFH, \_SB.PCI0.LNK1._CRS._Y0E._INT, IRH1)
CreateByteField (BUFH, 0x02, IRH2)
Store (Zero, IRH1)
Store (Zero, IRH2)
Store (PIRH, Local0)
If (LGreater (Local0, 0x00))
{
If (LGreater (Local0, 0x07))
{
Subtract (Local0, 0x08, Local0)
ShiftLeft (One, Local0, IRH2)
}
Else
{
Store (0x01, Local1)
ShiftLeft (Local1, Local0, IRH1)
}
}
Return (BUFH)
}
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x01, IRH1)
CreateByteField (Arg0, 0x02, IRH2)
If (LGreater (IRH2, Zero))
{
FindSetLeftBit (IRH2, Local0)
Decrement (Local0)
Add (Local0, 0x08, Local0)
}
Else
{
FindSetLeftBit (IRH1, Local0)
Decrement (Local0)
}
Store (One, ENR8)
Store (Zero, POLH)
Store (Local0, PIRH)
}
}
Device (ALKA)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x09)
Method (_STA, 0, NotSerialized)
{
If (LEqual (SBFL, 0x00))
{
Return (0x09)
}
If (LEqual (SBFL, 0x01))
{
If (LEqual (EIDE, 0x01))
{
Return (0x09)
}
Else
{
If (LEqual (ENAT, 0x0A))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
}
If (LEqual (SBFL, 0x02))
{
If (LEqual (EIDE, 0x01))
{
Return (0x09)
}
Else
{
If (LEqual (ENAT, 0x0A))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
}
If (LEqual (SBFL, 0x03))
{
If (LNotEqual (ATFL, 0x02))
{
If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Else
{
If (LEqual (\_SB.PCI0.PATA.ENAT, 0x0A))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
}
}
Method (_PRS, 0, NotSerialized)
{
Name (A37A, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{1,3,4,5,6,7,10,11,12,14,15}
})
Name (A47N, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, )
{
0x00000014,
}
})
If (LEqual (SBFL, 0x00))
{
Return (A37A)
}
If (LEqual (SBFL, 0x01))
{
Return (A47N)
}
If (LEqual (SBFL, 0x02))
{
Return (A47N)
}
If (LEqual (SBFL, 0x03))
{
Return (A47N)
}
}
Method (_DIS, 0, NotSerialized)
{
}
Method (_CRS, 0, NotSerialized)
{
Name (B37A, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y0F)
{}
})
CreateByteField (B37A, \_SB.PCI0.ALKA._CRS._Y0F._INT, IRB1)
CreateByteField (B37A, 0x02, IRB2)
Name (B47A, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, _Y10)
{
0x00000000,
}
})
CreateByteField (B47A, \_SB.PCI0.ALKA._CRS._Y10._INT, IRAI)
If (LEqual (SBFL, 0x00))
{
Return (B37A)
}
Else
{
Store (0x14, IRAI)
Return (B47A)
}
}
Method (_SRS, 1, NotSerialized)
{
}
}
Device (ALKB)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x0A)
Method (_STA, 0, NotSerialized)
{
If (LEqual (SBFL, 0x00))
{
And (IDEB, 0x34, Local0)
If (LEqual (Local0, 0x34))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
If (LEqual (SBFL, 0x01))
{
And (IDEB, 0x30, Local0)
If (LEqual (Local0, 0x30))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
If (LEqual (SBFL, 0x02))
{
And (IDEB, 0x36, Local0)
If (LEqual (Local0, 0x36))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
If (LEqual (SBFL, 0x03))
{
And (IDEB, 0x37, Local0)
If (LEqual (Local0, 0x37))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
}
Method (_PRS, 0, NotSerialized)
{
Name (A37B, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{1,3,4,5,6,7,10,11,12,14,15}
})
Name (A47B, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, )
{
0x00000015,
}
})
If (LEqual (SBFL, 0x00))
{
Return (A37B)
}
If (LEqual (SBFL, 0x01))
{
Return (A47B)
}
If (LEqual (SBFL, 0x02))
{
Return (A47B)
}
If (LEqual (SBFL, 0x03))
{
Return (A47B)
}
}
Method (_DIS, 0, NotSerialized)
{
}
Method (_CRS, 0, NotSerialized)
{
Name (B37B, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y11)
{}
})
CreateByteField (B37B, \_SB.PCI0.ALKB._CRS._Y11._INT, IRA1)
CreateByteField (B37B, 0x02, IRA2)
Name (B47B, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, _Y12)
{
0x00000000,
}
})
CreateByteField (B47B, \_SB.PCI0.ALKB._CRS._Y12._INT, IRBI)
If (LEqual (SBFL, 0x00))
{
Store (0x00, Local3)
Store (0x00, Local4)
And (PIBC, 0x0F, Local1)
If (LNotEqual (Local1, 0x00))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRA1)
Store (Local4, IRA2)
}
Return (B37B)
}
Else
{
Store (0x15, IRBI)
Return (B47B)
}
}
Method (_SRS, 1, NotSerialized)
{
If (LEqual (SBFL, 0x00))
{
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (PIBC, 0xF0, PIBC)
Or (PIBC, Local1, PIBC)
}
}
}
Device (ALKC)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x0B)
Method (_STA, 0, NotSerialized)
{
If (LEqual (EAMC, 0x03))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
Method (_PRS, 0, NotSerialized)
{
Name (A37C, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{1,3,4,5,6,7,10,11,12,14,15}
})
Name (A47C, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, )
{
0x00000016,
}
})
If (LEqual (SBFL, 0x00))
{
Return (A37C)
}
If (LEqual (SBFL, 0x01))
{
Return (A47C)
}
If (LEqual (SBFL, 0x02))
{
Return (A47C)
}
If (LEqual (SBFL, 0x03))
{
Return (A47C)
}
}
Method (_DIS, 0, NotSerialized)
{
}
Method (_CRS, 0, NotSerialized)
{
Name (B37C, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y13)
{}
})
CreateByteField (B37C, \_SB.PCI0.ALKC._CRS._Y13._INT, IRC1)
CreateByteField (B37C, 0x02, IRC2)
Name (B47C, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, _Y14)
{
0x00000000,
}
})
CreateByteField (B47C, \_SB.PCI0.ALKC._CRS._Y14._INT, IRCI)
If (LEqual (SBFL, 0x00))
{
Store (0x00, Local3)
Store (0x00, Local4)
And (PIBC, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNotEqual (Local1, 0x00))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRC1)
Store (Local4, IRC2)
}
Return (B37C)
}
Else
{
Store (0x16, IRCI)
Return (B47C)
}
}
Method (_SRS, 1, NotSerialized)
{
If (LEqual (SBFL, 0x00))
{
CreateByteField (Arg0, 0x01, IRC1)
CreateByteField (Arg0, 0x02, IRC2)
ShiftLeft (IRC2, 0x08, Local0)
Or (Local0, IRC1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (PIBC, 0x0F, PIBC)
ShiftLeft (Local1, 0x04, Local1)
Or (PIBC, Local1, PIBC)
}
}
}
Device (ALKD)
{
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x0C)
Method (_STA, 0, NotSerialized)
{
If (LEqual (SBFL, 0x01))
{
Return (0x09)
}
Else
{
If (LEqual (ELAN, 0x00))
{
Return (0x09)
}
Else
{
Return (0x0B)
}
}
}
Method (_PRS, 0, NotSerialized)
{
Name (A37D, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, )
{1,3,4,5,6,7,10,11,12,14,15}
})
Name (A47D, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, )
{
0x00000015,
}
})
Name (A77D, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, )
{
0x00000017,
}
})
If (LEqual (SBFL, 0x00))
{
Return (A37D)
}
If (LEqual (SBFL, 0x01))
{
Return (A47D)
}
If (LEqual (SBFL, 0x02))
{
Return (A77D)
}
If (LEqual (SBFL, 0x03))
{
Return (A77D)
}
}
Method (_DIS, 0, NotSerialized)
{
}
Method (_CRS, 0, NotSerialized)
{
Name (B37D, ResourceTemplate ()
{
IRQ (Level, ActiveLow, Shared, _Y15)
{}
})
CreateByteField (B37D, \_SB.PCI0.ALKD._CRS._Y15._INT, IRD1)
CreateByteField (B37D, 0x02, IRD2)
Name (B47D, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, )
{
0x00000015,
}
})
Name (B77D, ResourceTemplate ()
{
Interrupt (ResourceConsumer, Level, ActiveLow,
Shared, ,, _Y16)
{
0x00000000,
}
})
CreateByteField (B77D, \_SB.PCI0.ALKD._CRS._Y16._INT, IRDI)
If (LEqual (SBFL, 0x00))
{
Store (0x00, Local3)
Store (0x00, Local4)
And (PIRD, 0xF0, Local1)
ShiftRight (Local1, 0x04, Local1)
If (LNotEqual (Local1, 0x00))
{
If (LGreater (Local1, 0x07))
{
Subtract (Local1, 0x08, Local2)
ShiftLeft (One, Local2, Local4)
}
Else
{
If (LGreater (Local1, 0x00))
{
ShiftLeft (One, Local1, Local3)
}
}
Store (Local3, IRD1)
Store (Local4, IRD2)
}
Return (B37D)
}
If (LEqual (SBFL, 0x01))
{
Return (B47D)
}
If (LEqual (SBFL, 0x02))
{
Store (0x17, IRDI)
Return (B77D)
}
If (LEqual (SBFL, 0x03))
{
Store (0x17, IRDI)
Return (B77D)
}
}
Method (_SRS, 1, NotSerialized)
{
If (LEqual (SBFL, 0x00))
{
CreateByteField (Arg0, 0x01, IRD1)
CreateByteField (Arg0, 0x02, IRD2)
ShiftLeft (IRD2, 0x08, Local0)
Or (Local0, IRD1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00))
{
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
And (PIRD, 0x0F, PIRD)
ShiftLeft (Local1, 0x04, Local1)
Or (PIRD, Local1, PIRD)
}
}
}
Scope (\)
{
OperationRegion (\SCPP, SystemIO, 0x042F, 0x01)
Field (\SCPP, ByteAcc, NoLock, Preserve)
{
SMIP, 8
}
}
Method (\_SB.PCI0._INI, 0, NotSerialized)
{
If (STRC (\_OS, "Microsoft Windows"))
{
Store (0x56, SMIP)
}
Else
{
If (STRC (\_OS, "Microsoft Windows NT"))
{
Store (0x58, SMIP)
Store (0x00, OSFX)
Store (0x00, OSFL)
}
Else
{
Store (0x57, SMIP)
Store (0x02, OSFX)
Store (0x02, OSFL)
}
}
Store (0x00, SBFL)
If (LEqual (DEID, 0x3147))
{
Store (0x01, SBFL)
}
If (LEqual (DEID, 0x3177))
{
Store (0x02, SBFL)
}
If (LEqual (DEID, 0x3227))
{
Store (0x03, SBFL)
}
If (LEqual (DEID, 0x3287))
{
Store (0x04, SBFL)
}
Store (0x00, ATFL)
If (LEqual (BSAT, 0x01))
{
Store (0x02, ATFL)
}
Else
{
If (LEqual (EIDE, 0x01))
{
Store (0x02, ATFL)
}
Else
{
If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
{
Store (0x01, ATFL)
}
}
}
}
Scope (\)
{
Method (OSTP, 0, NotSerialized)
{
If (LEqual (OSFX, 0x01))
{
Store (0x56, SMIP)
}
If (LEqual (OSFX, 0x02))
{
Store (0x57, SMIP)
}
If (LEqual (OSFX, 0x00))
{
Store (0x58, SMIP)
}
}
}
Device (SYSR)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x01)
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0010, // Range Minimum
0x0010, // Range Maximum
0x01, // Alignment
0x10, // Length
)
IO (Decode16,
0x0022, // Range Minimum
0x0022, // Range Maximum
0x01, // Alignment
0x1E, // Length
)
IO (Decode16,
0x0044, // Range Minimum
0x0044, // Range Maximum
0x01, // Alignment
0x1C, // Length
)
IO (Decode16,
0x0062, // Range Minimum
0x0062, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IO (Decode16,
0x0065, // Range Minimum
0x0065, // Range Maximum
0x01, // Alignment
0x0B, // Length
)
IO (Decode16,
0x0074, // Range Minimum
0x0074, // Range Maximum
0x01, // Alignment
0x0C, // Length
)
IO (Decode16,
0x0091, // Range Minimum
0x0091, // Range Maximum
0x01, // Alignment
0x03, // Length
)
IO (Decode16,
0x00A2, // Range Minimum
0x00A2, // Range Maximum
0x01, // Alignment
0x1E, // Length
)
IO (Decode16,
0x00E0, // Range Minimum
0x00E0, // Range Maximum
0x01, // Alignment
0x10, // Length
)
IO (Decode16,
0x04D0, // Range Minimum
0x04D0, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IO (Decode16,
0x0294, // Range Minimum
0x0294, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IO (Decode16,
0x0290, // Range Minimum
0x0290, // Range Maximum
0x01, // Alignment
0x08, // Length
)
})
}
Device (PIC)
{
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0020, // Range Minimum
0x0020, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IO (Decode16,
0x00A0, // Range Minimum
0x00A0, // Range Maximum
0x01, // Alignment
0x02, // Length
)
IRQNoFlags ()
{2}
})
}
Device (DMA1)
{
Name (_HID, EisaId ("PNP0200"))
Name (_CRS, ResourceTemplate ()
{
DMA (Compatibility, BusMaster, Transfer8, )
{4}
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x10, // Length
)
IO (Decode16,
0x0080, // Range Minimum
0x0080, // Range Maximum
0x01, // Alignment
0x11, // Length
)
IO (Decode16,
0x0094, // Range Minimum
0x0094, // Range Maximum
0x01, // Alignment
0x0C, // Length
)
IO (Decode16,
0x00C0, // Range Minimum
0x00C0, // Range Maximum
0x01, // Alignment
0x20, // Length
)
})
}
Device (TMR)
{
Name (_HID, EisaId ("PNP0100"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0040, // Range Minimum
0x0040, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IRQNoFlags ()
{0}
})
}
Device (RTC)
{
Name (_HID, EisaId ("PNP0B00"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0070, // Range Minimum
0x0070, // Range Maximum
0x04, // Alignment
0x04, // Length
)
IRQNoFlags ()
{8}
})
}
Device (SPKR)
{
Name (_HID, EisaId ("PNP0800"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0061, // Range Minimum
0x0061, // Range Maximum
0x01, // Alignment
0x01, // Length
)
})
}
Device (COPR)
{
Name (_HID, EisaId ("PNP0C04"))
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x00F0, // Range Minimum
0x00F0, // Range Maximum
0x01, // Alignment
0x10, // Length
)
IRQNoFlags ()
{13}
})
}
Scope (\)
{
OperationRegion (WIN1, SystemIO, 0x2E, 0x02)
Field (WIN1, ByteAcc, NoLock, Preserve)
{
INDP, 8,
DATA, 8
}
IndexField (INDP, DATA, ByteAcc, NoLock, Preserve)
{
Offset (0x02),
CFG, 8,
Offset (0x07),
LDN, 8,
Offset (0x20),
IDHI, 8,
IDLO, 8,
POWC, 8,
Offset (0x29),
CR29, 8,
Offset (0x30),
ACTR, 8,
Offset (0x60),
IOAH, 8,
IOAL, 8,
IO2H, 8,
IO2L, 8,
Offset (0x70),
INTR, 8,
Offset (0x72),
INT1, 8,
Offset (0x74),
DMCH, 8,
Offset (0xC0),
GP40, 8,
Offset (0xF0),
CRF0, 8,
CRF1, 8,
CRF2, 8,
CRF3, 8,
CRF4, 8,
CRF5, 8,
CRF6, 8,
CRF7, 8,
CRF8, 8
}
Method (ENFG, 0, NotSerialized)
{
Store (0x87, INDP)
Store (0x87, INDP)
}
Method (EXFG, 0, NotSerialized)
{
Store (0xAA, INDP)
}
}
Device (UAR1)
{
Name (_HID, EisaId ("PNP0501"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
ENFG ()
Store (0x02, LDN)
If (ACTR)
{
EXFG ()
Return (0x0F)
}
Else
{
If (LOr (IOAH, IOAL))
{
EXFG ()
Return (0x0D)
}
Else
{
EXFG ()
Return (0x00)
}
}
EXFG ()
}
Method (_DIS, 0, NotSerialized)
{
ENFG ()
Store (0x02, LDN)
Store (Zero, ACTR)
EXFG ()
DISD (0x00)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF1, ResourceTemplate ()
{
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x08, // Length
_Y17)
IRQNoFlags (_Y18)
{}
})
CreateByteField (BUF1, \_SB.PCI0.UAR1._CRS._Y17._MIN, IOLO)
CreateByteField (BUF1, 0x03, IOHI)
CreateByteField (BUF1, \_SB.PCI0.UAR1._CRS._Y17._MAX, IORL)
CreateByteField (BUF1, 0x05, IORH)
CreateWordField (BUF1, \_SB.PCI0.UAR1._CRS._Y18._INT, IRQW)
ENFG ()
Store (0x02, LDN)
Store (IOAL, IOLO)
Store (IOAL, IORL)
Store (IOAH, IOHI)
Store (IOAH, IORH)
Store (One, Local0)
ShiftLeft (Local0, INTR, IRQW)
EXFG ()
Return (BUF1)
}
Name (_PRS, ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16,
0x03F8, // Range Minimum
0x03F8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x02F8, // Range Minimum
0x02F8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x03E8, // Range Minimum
0x03E8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x02E8, // Range Minimum
0x02E8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
EndDependentFn ()
})
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, IOLO)
CreateByteField (Arg0, 0x03, IOHI)
CreateWordField (Arg0, 0x02, IOAD)
CreateWordField (Arg0, 0x09, IRQW)
ENFG ()
Store (0x02, LDN)
Store (One, ACTR)
Store (IOLO, IOAL)
Store (IOHI, IOAH)
FindSetRightBit (IRQW, Local0)
Subtract (Local0, 0x01, INTR)
EXFG ()
CKIO (IOAD, 0x00)
}
}
Device (UAR2)
{
Name (_HID, EisaId ("PNP0501"))
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
ENFG ()
Store (0x03, LDN)
And (CRF1, 0x30, Local0)
If (LNotEqual (Local0, 0x10))
{
If (ACTR)
{
EXFG ()
Return (0x0F)
}
Else
{
If (LOr (IOAH, IOAL))
{
EXFG ()
Return (0x0D)
}
Else
{
EXFG ()
Return (0x00)
}
}
}
Else
{
EXFG ()
Return (0x00)
}
}
Method (_DIS, 0, NotSerialized)
{
ENFG ()
Store (0x03, LDN)
And (CRF1, 0x38, Local0)
If (LEqual (Local0, 0x00))
{
Store (Zero, ACTR)
}
EXFG ()
DISD (0x01)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF2, ResourceTemplate ()
{
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x08, // Length
_Y19)
IRQNoFlags (_Y1A)
{4}
})
CreateByteField (BUF2, \_SB.PCI0.UAR2._CRS._Y19._MIN, IOLO)
CreateByteField (BUF2, 0x03, IOHI)
CreateByteField (BUF2, \_SB.PCI0.UAR2._CRS._Y19._MAX, IORL)
CreateByteField (BUF2, 0x05, IORH)
CreateWordField (BUF2, \_SB.PCI0.UAR2._CRS._Y1A._INT, IRQW)
ENFG ()
Store (0x03, LDN)
Store (IOAL, IOLO)
Store (IOAL, IORL)
Store (IOAH, IOHI)
Store (IOAH, IORH)
Store (One, Local0)
ShiftLeft (Local0, INTR, IRQW)
EXFG ()
Return (BUF2)
}
Name (_PRS, ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16,
0x03F8, // Range Minimum
0x03F8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x02F8, // Range Minimum
0x02F8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x03E8, // Range Minimum
0x03E8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x02E8, // Range Minimum
0x02E8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
EndDependentFn ()
})
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, IOLO)
CreateByteField (Arg0, 0x03, IOHI)
CreateWordField (Arg0, 0x02, IOAD)
CreateWordField (Arg0, 0x09, IRQW)
ENFG ()
Store (0x03, LDN)
Store (One, ACTR)
Store (IOLO, IOAL)
Store (IOHI, IOAH)
FindSetRightBit (IRQW, Local0)
Subtract (Local0, 0x01, INTR)
EXFG ()
CKIO (IOAD, 0x01)
}
}
Device (IRDA)
{
Name (_HID, EisaId ("PNP0510"))
Method (_STA, 0, NotSerialized)
{
ENFG ()
Store (0x03, LDN)
And (CRF1, 0x30, Local0)
If (LEqual (Local0, 0x10))
{
If (ACTR)
{
EXFG ()
Return (0x0F)
}
Else
{
If (LOr (IOAH, IOAL))
{
EXFG ()
Return (0x0D)
}
Else
{
EXFG ()
Return (0x00)
}
}
}
Else
{
EXFG ()
Return (0x00)
}
}
Method (_DIS, 0, NotSerialized)
{
If (LEqual (DISE, 0x01))
{
ENFG ()
Store (0x03, LDN)
And (CRF1, 0x38, Local0)
If (LNotEqual (Local0, 0x00))
{
Store (Zero, ACTR)
}
EXFG ()
DISD (0x01)
}
Store (Local0, Local0)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF4, ResourceTemplate ()
{
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x08, // Length
_Y1B)
IRQNoFlags (_Y1C)
{}
})
CreateByteField (BUF4, \_SB.PCI0.IRDA._CRS._Y1B._MIN, IOLO)
CreateByteField (BUF4, 0x03, IOHI)
CreateByteField (BUF4, \_SB.PCI0.IRDA._CRS._Y1B._MAX, IORL)
CreateByteField (BUF4, 0x05, IORH)
CreateWordField (BUF4, \_SB.PCI0.IRDA._CRS._Y1C._INT, IRQW)
ENFG ()
Store (0x03, LDN)
Store (IOAL, IOLO)
Store (IOAL, IORL)
Store (IOAH, IOHI)
Store (IOAH, IORH)
ShiftLeft (0x01, INTR, IRQW)
EXFG ()
Return (BUF4)
}
Name (_PRS, ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16,
0x03F8, // Range Minimum
0x03F8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x02F8, // Range Minimum
0x02F8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x03E8, // Range Minimum
0x03E8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x02E8, // Range Minimum
0x02E8, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
EndDependentFn ()
})
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, IOLO)
CreateByteField (Arg0, 0x03, IOHI)
CreateWordField (Arg0, 0x02, IOAD)
CreateWordField (Arg0, 0x09, IRQW)
ENFG ()
Store (0x03, LDN)
Store (One, ACTR)
Store (IOLO, IOAL)
Store (IOHI, IOAH)
FindSetRightBit (IRQW, Local0)
Subtract (Local0, 0x01, INTR)
EXFG ()
CKIO (IOAD, 0x01)
}
}
Device (LPT1)
{
Name (_HID, EisaId ("PNP0400"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
ENFG ()
Store (0x01, LDN)
And (CRF0, 0x02, Local0)
If (LNotEqual (Local0, 0x02))
{
If (ACTR)
{
EXFG ()
Return (0x0F)
}
Else
{
If (LOr (IOAH, IOAL))
{
EXFG ()
Return (0x0D)
}
Else
{
EXFG ()
Return (0x00)
}
}
}
Else
{
EXFG ()
Return (0x00)
}
}
Method (_DIS, 0, NotSerialized)
{
ENFG ()
Store (0x01, LDN)
Store (Zero, ACTR)
EXFG ()
DISD (0x02)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF5, ResourceTemplate ()
{
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x08, // Length
_Y1D)
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x04, // Length
_Y1E)
IRQNoFlags (_Y1F)
{}
})
CreateByteField (BUF5, \_SB.PCI0.LPT1._CRS._Y1D._MIN, IOLO)
CreateByteField (BUF5, 0x03, IOHI)
CreateByteField (BUF5, \_SB.PCI0.LPT1._CRS._Y1D._MAX, IORL)
CreateByteField (BUF5, 0x05, IORH)
CreateByteField (BUF5, \_SB.PCI0.LPT1._CRS._Y1D._LEN, IOLE)
CreateByteField (BUF5, \_SB.PCI0.LPT1._CRS._Y1E._MIN, IO21)
CreateByteField (BUF5, 0x0B, IO22)
CreateByteField (BUF5, \_SB.PCI0.LPT1._CRS._Y1E._MAX, IO23)
CreateByteField (BUF5, 0x0D, IO24)
CreateWordField (BUF5, \_SB.PCI0.LPT1._CRS._Y1F._INT, IRQW)
ENFG ()
Store (0x01, LDN)
Store (IOAL, IOLO)
Store (IOLO, IORL)
Store (IOAH, IOHI)
Store (IOHI, IORH)
Store (IOAL, IO21)
Store (IOAL, IO23)
Add (IOAH, 0x04, IO22)
Add (IOAH, 0x04, IO24)
If (LEqual (IOLO, 0xBC))
{
Store (0x04, IOLE)
}
Else
{
Store (0x08, IOLE)
}
Store (One, Local0)
Store (INTR, Local5)
ShiftLeft (Local0, Local5, IRQW)
Store (One, ACTR)
EXFG ()
Return (BUF5)
}
Name (_PRS, ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16,
0x0378, // Range Minimum
0x0378, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IO (Decode16,
0x0778, // Range Minimum
0x0778, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x0278, // Range Minimum
0x0278, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IO (Decode16,
0x0678, // Range Minimum
0x0678, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x03BC, // Range Minimum
0x03BC, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IO (Decode16,
0x03BC, // Range Minimum
0x03BC, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
}
EndDependentFn ()
})
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, IOLO)
CreateByteField (Arg0, 0x03, IOHI)
CreateWordField (Arg0, 0x02, IOAD)
CreateByteField (Arg0, 0x04, IORL)
CreateByteField (Arg0, 0x05, IORH)
CreateWordField (Arg0, 0x11, IRQW)
ENFG ()
Store (0x01, LDN)
Store (One, ACTR)
Store (IOLO, IOAL)
Store (IOHI, IOAH)
FindSetLeftBit (IRQW, Local0)
Subtract (Local0, 0x01, Local0)
Store (Local0, INTR)
EXFG ()
CKIO (IOAD, 0x02)
}
}
Device (ECP1)
{
Name (_HID, EisaId ("PNP0401"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
ENFG ()
Store (0x01, LDN)
And (CRF0, 0x02, Local0)
If (LEqual (Local0, 0x02))
{
If (ACTR)
{
EXFG ()
Return (0x0F)
}
Else
{
If (LOr (IOAH, IOAL))
{
EXFG ()
Return (0x0D)
}
Else
{
EXFG ()
Return (0x00)
}
}
}
Else
{
EXFG ()
Return (0x00)
}
}
Method (_DIS, 0, NotSerialized)
{
ENFG ()
Store (0x01, LDN)
Store (Zero, ACTR)
SLDM (DMCH, 0x04)
EXFG ()
DISD (0x02)
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF6, ResourceTemplate ()
{
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x08, // Length
_Y20)
IO (Decode16,
0x0000, // Range Minimum
0x0000, // Range Maximum
0x01, // Alignment
0x04, // Length
_Y21)
IRQNoFlags (_Y22)
{}
DMA (Compatibility, NotBusMaster, Transfer8, _Y23)
{}
})
CreateByteField (BUF6, \_SB.PCI0.ECP1._CRS._Y20._MIN, IOLO)
CreateByteField (BUF6, 0x03, IOHI)
CreateByteField (BUF6, \_SB.PCI0.ECP1._CRS._Y20._MAX, IORL)
CreateByteField (BUF6, 0x05, IORH)
CreateByteField (BUF6, \_SB.PCI0.ECP1._CRS._Y20._LEN, IOLE)
CreateByteField (BUF6, \_SB.PCI0.ECP1._CRS._Y21._MIN, IOEL)
CreateByteField (BUF6, 0x0B, IOEH)
CreateByteField (BUF6, \_SB.PCI0.ECP1._CRS._Y21._MAX, IOML)
CreateByteField (BUF6, 0x0D, IOMH)
CreateWordField (BUF6, \_SB.PCI0.ECP1._CRS._Y22._INT, IRQW)
CreateByteField (BUF6, \_SB.PCI0.ECP1._CRS._Y23._DMA, DMAC)
ENFG ()
Store (0x01, LDN)
Store (One, ACTR)
Store (IOAL, Local2)
Store (Local2, IOLO)
Store (IOAH, Local3)
Store (Local3, IOHI)
Or (Local3, 0x04, Local3)
Store (Local3, IOEH)
Store (Local3, IOMH)
Store (IOLO, IORL)
Store (IOLO, IOEL)
Store (IOLO, IOML)
Store (IOHI, IORH)
If (LEqual (IOLO, 0xBC))
{
Store (0x04, IOLE)
}
Else
{
Store (0x08, IOLE)
}
Store (One, Local0)
Store (INTR, Local5)
ShiftLeft (Local0, Local5, IRQW)
Store (One, Local0)
Store (DMCH, Local5)
ShiftLeft (Local0, Local5, DMAC)
EXFG ()
Return (BUF6)
}
Name (_PRS, ResourceTemplate ()
{
StartDependentFnNoPri ()
{
IO (Decode16,
0x0378, // Range Minimum
0x0378, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IO (Decode16,
0x0778, // Range Minimum
0x0778, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
DMA (Compatibility, NotBusMaster, Transfer8, )
{0,1,3}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x0278, // Range Minimum
0x0278, // Range Maximum
0x01, // Alignment
0x08, // Length
)
IO (Decode16,
0x0678, // Range Minimum
0x0678, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
DMA (Compatibility, NotBusMaster, Transfer8, )
{0,1,3}
}
StartDependentFnNoPri ()
{
IO (Decode16,
0x03BC, // Range Minimum
0x03BC, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IO (Decode16,
0x07BC, // Range Minimum
0x07BC, // Range Maximum
0x01, // Alignment
0x04, // Length
)
IRQNoFlags ()
{3,4,5,7,9,10,11,12}
DMA (Compatibility, NotBusMaster, Transfer8, )
{0,1,3}
}
EndDependentFn ()
})
Method (_SRS, 1, NotSerialized)
{
CreateByteField (Arg0, 0x02, IOLO)
CreateByteField (Arg0, 0x03, IOHI)
CreateWordField (Arg0, 0x02, IOAD)
CreateWordField (Arg0, 0x11, IRQW)
CreateByteField (Arg0, 0x14, DMAC)
ENFG ()
Store (0x01, LDN)
Store (One, ACTR)
Store (IOLO, IOAL)
Store (IOHI, IOAH)
FindSetLeftBit (IRQW, Local0)
Subtract (Local0, 0x01, Local0)
Store (Local0, INTR)
FindSetLeftBit (DMAC, Local1)
Store (DMCH, Local0)
Subtract (Local1, 0x01, DMCH)
SLDM (Local0, DMCH)
EXFG ()
CKIO (IOAD, 0x02)
}
}
OperationRegion (KBCT, SystemIO, 0x60, 0x05)
Field (KBCT, ByteAcc, NoLock, Preserve)
{
P060, 8,
Offset (0x04),
P064, 8
}
Device (PS2M)
{
Name (_HID, EisaId ("PNP0F13"))
Method (_STA, 0, NotSerialized)
{
If (LEqual (PS2F, 0x00))
{
Return (0x0F)
}
Else
{
Return (0x00)
}
}
Method (_CRS, 0, NotSerialized)
{
Name (BUF1, ResourceTemplate ()
{
IRQNoFlags ()
{12}
})
Name (BUF2, ResourceTemplate ()
{
IO (Decode16,
0x0060, // Range Minimum
0x0060, // Range Maximum
0x01, // Alignment
0x01, // Length
)
IO (Decode16,
0x0064, // Range Minimum
0x0064, // Range Maximum
0x01, // Alignment
0x01, // Length
)
IRQNoFlags ()
{12}
})
If (LEqual (KBDI, 0x01))
{
If (LEqual (OSFL, 0x02))
{
Return (BUF1)
}
If (LEqual (OSFL, 0x01))
{
Return (BUF1)
}
Else
{
Return (BUF2)
}
}
Else
{
Return (BUF1)
}
}
}
Device (PS2K)
{
Name (_HID, EisaId ("PNP0303"))
Name (_CID, EisaId ("PNP030B"))
Method (_STA, 0, NotSerialized)
{
If (LEqual (KBDI, 0x01))
{
Return (0x00)
}
Else
{
Return (0x0F)
}
}
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0060, // Range Minimum
0x0060, // Range Maximum
0x01, // Alignment
0x01, // Length
)
IO (Decode16,
0x0064, // Range Minimum
0x0064, // Range Maximum
0x01, // Alignment
0x01, // Length
)
IRQNoFlags ()
{1}
})
}
Device (PSMR)
{
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x03)
Method (_STA, 0, NotSerialized)
{
If (LEqual (KBDI, 0x00))
{
Return (0x00)
}
If (LEqual (PS2F, 0x00))
{
If (LEqual (OSFL, 0x02))
{
Return (0x0F)
}
If (LEqual (OSFL, 0x01))
{
Return (0x0F)
}
Return (0x00)
}
Return (0x00)
}
Name (_CRS, ResourceTemplate ()
{
IO (Decode16,
0x0060, // Range Minimum
0x0060, // Range Maximum
0x01, // Alignment
0x01, // Length
)
IO (Decode16,
0x0064, // Range Minimum
0x0064, // Range Maximum
0x01, // Alignment
0x01, // Length
)
})
}
Method (\_SB.PCI0.UAR1._PRW, 0, NotSerialized)
{
Return (Package (0x02)
{
0x08,
0x05
})
}
}
}
}
From: Jukka Ruohonen <jruohonen@iki.fi>
To: gnats-bugs@NetBSD.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA VT-310DP motherboard
Date: Sun, 15 Aug 2010 07:05:42 +0300
Thanks.
Nothing wrong there that I could see. Must be something else.
From: Andrius V <vezhlys@gmail.com>
To: gnats-bugs@netbsd.org
Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Mon, 16 Aug 2010 09:39:21 +0300
Can I provide some more information then? I can connect it through
serial interface and try to debug boot process however i don't have
enough knowledge to understand the output (and I don't know if it cant
provide anything useful). It seems that at some point it goes into
infinitive loop (but I might be wrong). This problem exists from 5.0
version and netbsd current still can't freezes at the same point.
On Sun, Aug 15, 2010 at 7:10 AM, Jukka Ruohonen <jruohonen@iki.fi> wrote:
> The following reply was made to PR port-i386/41267; it has been noted by =
GNATS.
>
> From: Jukka Ruohonen <jruohonen@iki.fi>
> To: gnats-bugs@NetBSD.org
> Cc:
> Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA V=
T-310DP motherboard
> Date: Sun, 15 Aug 2010 07:05:42 +0300
>
> =C2=A0Thanks.
>
> =C2=A0Nothing wrong there that I could see. Must be something else.
>
>
From: Andrius V <vezhlys@gmail.com>
To: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org, vezhlys@gmail.com, gnats-bugs@netbsd.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Wed, 2 Feb 2011 22:26:32 +0200
Hello NetBSD developers,
I investigated a little bit a boot process and I found a place where
exactly it "hangs". In reality the system doesn't hang but it is
trapped into infinitive loop in tsc_read_bp function from tsc.c which
is called from tsc_sync_bp and finally this one is called from
cpu_boot_secondary in cpu.c. The exact loop where it loops endlessly
in tsc_read_bp function is
/* Wait for the results to come in. */
while (tsc_sync_cpu =3D=3D ci) {
x86_pause();
}
I don't have enough knowledge to understand why expected results
didn't come in (by comment) and what processes didn't work. Maybe,
second cpu wasn't still initialized by this moment? Will this
information help to understand the problem or guide to some more
investigation? Thanks.
On Mon, Aug 16, 2010 at 9:40 AM, Andrius V <vezhlys@gmail.com> wrote:
> The following reply was made to PR port-i386/41267; it has been noted by =
GNATS.
>
> From: Andrius V <vezhlys@gmail.com>
> To: gnats-bugs@netbsd.org
> Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0netbsd-bugs@netbsd.org
> Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
> =C2=A0VT-310DP motherboard
> Date: Mon, 16 Aug 2010 09:39:21 +0300
>
> =C2=A0Can I provide some more information then? I can connect it through
> =C2=A0serial interface and try to debug boot process however i don't have
> =C2=A0enough knowledge to understand the output (and I don't know if it c=
ant
> =C2=A0provide anything useful). It seems that at some point it goes into
> =C2=A0infinitive loop (but I might be wrong). This problem exists from 5.=
0
> =C2=A0version and netbsd current still can't freezes at the same point.
>
> =C2=A0On Sun, Aug 15, 2010 at 7:10 AM, Jukka Ruohonen <jruohonen@iki.fi> =
wrote:
> =C2=A0> The following reply was made to PR port-i386/41267; it has been n=
oted by =3D
> =C2=A0GNATS.
> =C2=A0>
> =C2=A0> From: Jukka Ruohonen <jruohonen@iki.fi>
> =C2=A0> To: gnats-bugs@NetBSD.org
> =C2=A0> Cc:
> =C2=A0> Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU =
in VIA V=3D
> =C2=A0T-310DP motherboard
> =C2=A0> Date: Sun, 15 Aug 2010 07:05:42 +0300
> =C2=A0>
> =C2=A0> =3DC2=3DA0Thanks.
> =C2=A0>
> =C2=A0> =3DC2=3DA0Nothing wrong there that I could see. Must be something=
else.
> =C2=A0>
> =C2=A0>
>
>
From: Andrius V <vezhlys@gmail.com>
To: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org, vezhlys@gmail.com, gnats-bugs@netbsd.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Thu, 3 Feb 2011 00:09:24 +0200
Just correction tsc_sync_bp is called from cpu_start_secondary not
cpu_boot_secondary.
On Wed, Feb 2, 2011 at 10:30 PM, Andrius V <vezhlys@gmail.com> wrote:
> The following reply was made to PR port-i386/41267; it has been noted by =
GNATS.
>
> From: Andrius V <vezhlys@gmail.com>
> To: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0netbsd-bugs@netbsd.org, vezhlys@gmail.com, gna=
ts-bugs@netbsd.org
> Cc:
> Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
> =C2=A0VT-310DP motherboard
> Date: Wed, 2 Feb 2011 22:26:32 +0200
>
> =C2=A0Hello NetBSD developers,
>
> =C2=A0I investigated a little bit a boot process and I found a place wher=
e
> =C2=A0exactly it "hangs". In reality the system doesn't hang but it is
> =C2=A0trapped into infinitive loop in tsc_read_bp function from tsc.c whi=
ch
> =C2=A0is called from tsc_sync_bp and finally this one is called from
> =C2=A0cpu_boot_secondary in cpu.c. The exact loop where it loops endlessl=
y
> =C2=A0in tsc_read_bp function is
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Wait for the results to come in. */
> =C2=A0 =C2=A0 =C2=A0 =C2=A0while (tsc_sync_cpu =3D3D=3D3D ci) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0x86_pause();
> =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>
> =C2=A0I don't have enough knowledge to understand why expected results
> =C2=A0didn't come in (by comment) and what processes didn't work. Maybe,
> =C2=A0second cpu wasn't still initialized by this moment? Will this
> =C2=A0information help to understand the problem or guide to some more
> =C2=A0investigation? Thanks.
>
>
>
> =C2=A0On Mon, Aug 16, 2010 at 9:40 AM, Andrius V <vezhlys@gmail.com> wrot=
e:
> =C2=A0> The following reply was made to PR port-i386/41267; it has been n=
oted by =3D
> =C2=A0GNATS.
> =C2=A0>
> =C2=A0> From: Andrius V <vezhlys@gmail.com>
> =C2=A0> To: gnats-bugs@netbsd.org
> =C2=A0> Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
> =C2=A0> =3DC2=3DA0 =3DC2=3DA0 =3DC2=3DA0 =3DC2=3DA0netbsd-bugs@netbsd.org
> =C2=A0> Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU =
in VIA
> =C2=A0> =3DC2=3DA0VT-310DP motherboard
> =C2=A0> Date: Mon, 16 Aug 2010 09:39:21 +0300
> =C2=A0>
> =C2=A0> =3DC2=3DA0Can I provide some more information then? I can connect=
it through
> =C2=A0> =3DC2=3DA0serial interface and try to debug boot process however =
i don't have
> =C2=A0> =3DC2=3DA0enough knowledge to understand the output (and I don't =
know if it c=3D
> =C2=A0ant
> =C2=A0> =3DC2=3DA0provide anything useful). It seems that at some point i=
t goes into
> =C2=A0> =3DC2=3DA0infinitive loop (but I might be wrong). This problem ex=
ists from 5.=3D
> =C2=A00
> =C2=A0> =3DC2=3DA0version and netbsd current still can't freezes at the s=
ame point.
> =C2=A0>
> =C2=A0> =3DC2=3DA0On Sun, Aug 15, 2010 at 7:10 AM, Jukka Ruohonen <jruoho=
nen@iki.fi> =3D
> =C2=A0wrote:
> =C2=A0> =3DC2=3DA0> The following reply was made to PR port-i386/41267; i=
t has been n=3D
> =C2=A0oted by =3D3D
> =C2=A0> =3DC2=3DA0GNATS.
> =C2=A0> =3DC2=3DA0>
> =C2=A0> =3DC2=3DA0> From: Jukka Ruohonen <jruohonen@iki.fi>
> =C2=A0> =3DC2=3DA0> To: gnats-bugs@NetBSD.org
> =C2=A0> =3DC2=3DA0> Cc:
> =C2=A0> =3DC2=3DA0> Subject: Re: port-i386/41267: 5.0 RC4 does not detect=
second CPU =3D
> =C2=A0in VIA V=3D3D
> =C2=A0> =3DC2=3DA0T-310DP motherboard
> =C2=A0> =3DC2=3DA0> Date: Sun, 15 Aug 2010 07:05:42 +0300
> =C2=A0> =3DC2=3DA0>
> =C2=A0> =3DC2=3DA0> =3D3DC2=3D3DA0Thanks.
> =C2=A0> =3DC2=3DA0>
> =C2=A0> =3DC2=3DA0> =3D3DC2=3D3DA0Nothing wrong there that I could see. M=
ust be something=3D
> =C2=A0else.
> =C2=A0> =3DC2=3DA0>
> =C2=A0> =3DC2=3DA0>
> =C2=A0>
> =C2=A0>
>
>
From: Andrius V <vezhlys@gmail.com>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Mon, 11 Apr 2011 15:57:46 +0300
Didn't sent to gnats-bugs (retry)
Hello once again,
I investigated the problem more and I found the exact place where
something went wrong... I realized that tsc_read_bp function waits for
results whose come from tsc_post_ap (functions from tsc.c). I printed
some text after every step in tsc_post_ap and found that it stopped
printing before this line:
/* Post result. Ensure the whole value goes out atomically. */
(void)atomic_swap_64(&tsc_sync_val, tsc);
I commented this line (I know that it is not a solution at all but I
just wanted to be sure) and to my surprise the second cpu started...
Unfortunately one more problem appeared with via ide drivers
(viaide0:0:0: lost interrupt), but I successfully booted NetBSD
without acpi support (-2vx). I posted dmesg below. If somebody will
help me to understand how atomic_swap_64 works on i386 architecture I
might try to localize the problem even more...
What is more I found that x86_ipi_init: ESR 00000040 problem comes
after first i82489_writereg(LAPIC_ESR, 0); call (so it wasn't related
problem). If I add two function i82489_writereg(LAPIC_ESR, 0) calls
one after another in x86_ipi_init then problem disappears and never
reappears. If I comment this line then I am getting the same error in
x86_ipi_startup function.
dmesg represents this two changes I described (commented
atomic_swap_64 line and added second i82489_writereg(LAPIC_ESR, 0);
call in x86_ipi_init), -2vx arguments used:
rbus: rbus_min_start set to 0x80000000
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 5.99.48 (VT-3102) #58: Mon Apr 11 04:50:22 EEST 2011
andrius@agraphic-vt310dp.VIDANDRIUS:/usr/src/sys/arch/i386/compile/VT-3102
total memory = 1981 MB
avail memory = 1935 MB
Prep module path=ffs len=230310 pa=c4d000
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
BIOS32 rev. 0 found at 0xfa2a0
SMBIOS rev. 2.3 @ 0xf0000 (37 entries)
VIA Technologies, Inc. CN400-8237 ( )
mainbus0 (root)
mainbus0: Intel MP Specification (Version 1.4) (OEM00000 PROD00000000)
cpu0 at mainbus0 apid 0cpu0: calibrating local timer
cpu0: apic clock running at 133 MHz
timecounter: Timecounter "lapic" frequency 133032544 Hz quality -100
: VIA Nehemiah, id 0x69a
cpu0: PAT enabled
cpu1 at mainbus0 apid 1: VIA Nehemiah, id 0x69a
cpu1: PAT enabled
mpbios: bus 0 is type PCI
mpbios: bus 1 is type PCI
mpbios: bus 2 is type ISA
ioapic0 at mainbus0 apid 2: pa 0xfec00000, version 3, 24 pins
ioapic0: misconfigured as apic 0
ioapic0: remapped to apic 2
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0: vendor 0x1106 product 0x0259 (rev. 0x00)
agp0 at pchb0 (v3): aperture at 0xe8000000, size 0x8000000
pchb1 at pci0 dev 0 function 1: vendor 0x1106 product 0x1259 (rev. 0x00)
pchb2 at pci0 dev 0 function 2: vendor 0x1106 product 0x2259 (rev. 0x00)
pchb3 at pci0 dev 0 function 3: vendor 0x1106 product 0x3259 (rev. 0x00)
pchb4 at pci0 dev 0 function 4: vendor 0x1106 product 0x4259 (rev. 0x00)
pchb5 at pci0 dev 0 function 7: vendor 0x1106 product 0x7259 (rev. 0x00)
ppb0 at pci0 dev 1 function 0: vendor 0x1106 product 0xb198 (rev. 0x00)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
vga1 at pci1 dev 0 function 0: vendor 0x1106 product 0x3118 (rev. 0x02)
wsdisplay0 at vga1 kbdmux 1
wsmux1: connecting to wsdisplay0
viadrm0 at vga1pci_mem_find: void region
pci_mem_find: void region
pci_mem_find: void region
pci_mem_find: void region
: VIA CN400 / PM8X0
viadrm0: AGP at 0xe8000000 128MB
viadrm0: Initialized via 2.11.1 20070202
fxp0 at pci0 dev 9 function 0: i82551 Ethernet, rev 16
fxp0: interrupting at ioapic0 pin 17
fxp0: Ethernet address 00:e0:81:59:68:e5
inphy0 at fxp0 phy 1: i82555 10/100 media interface, rev. 4
inphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
vge0 at pci0 dev 10 function 0: VIA VT612X Gigabit Ethernet (rev. 0x11)
vge0: interrupting at ioapic0 pin 18
vge0: Ethernet address: 00:e0:81:59:68:e3
ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
1000baseT-FDX, auto
pci_mem_find: expected type mem, found i/o
viaide0 at pci0 dev 15 function 0: VIA Technologies VT8237 SATA
Controller (rev. 0x80)
viaide0: bus-master DMA support present
viaide0: primary channel wired to native-PCI mode
viaide0: using ioapic0 pin 20 for native-PCI interrupt
atabus0 at viaide0 channel 0
viaide0: secondary channel wired to native-PCI mode
atabus1 at viaide0 channel 1
uhci0 at pci0 dev 16 function 0: vendor 0x1106 product 0x3038 (rev. 0x81)
uhci0: interrupting at ioapic0 pin 21
usb0 at uhci0: USB revision 1.0
usb0: WARNING: power management not supported
uhci1 at pci0 dev 16 function 1: vendor 0x1106 product 0x3038 (rev. 0x81)
uhci1: interrupting at ioapic0 pin 21
usb1 at uhci1: USB revision 1.0
usb1: WARNING: power management not supported
uhci2 at pci0 dev 16 function 2: vendor 0x1106 product 0x3038 (rev. 0x81)
uhci2: interrupting at ioapic0 pin 21
usb2 at uhci2: USB revision 1.0
usb2: WARNING: power management not supported
uhci3 at pci0 dev 16 function 3: vendor 0x1106 product 0x3038 (rev. 0x81)
uhci3: interrupting at ioapic0 pin 21
usb3 at uhci3: USB revision 1.0
usb3: WARNING: power management not supported
ehci0 at pci0 dev 16 function 4: vendor 0x1106 product 0x3104 (rev. 0x86)
ehci0: interrupting at ioapic0 pin 21
ehci0: dropped intr workaround enabled
ehci0: BIOS refuses to give up ownership, using force
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1 uhci2 uhci3
usb4 at ehci0: USB revision 2.0
usb4: WARNING: power management not supported
viapcib0 at pci0 dev 17 function 0: vendor 0x1106 product 0x3227 (rev. 0x00)
viapcib0: SMBus found at 0x500 (revision 0x0)
iic0 at viapcib0: I2C bus
auvia0 at pci0 dev 17 function 5: VIA Technologies VT8237 AC'97 Audio (rev 0x60)
auvia0: interrupting at ioapic0 pin 22
auvia0: ac97: VIA Technologies VT1616i codec; headphone, 18 bit DAC,
18 bit ADC, KS Waves 3D
auvia0: ac97: ext id 0x1c1<LDAC,SDAC,CDAC,VRA>
audio0 at auvia0: full duplex, playback, capture, mmap, independent
vr0 at pci0 dev 18 function 0: vendor 0x1106 product 0x3065 (rev. 0x78)
vr0: interrupting at ioapic0 pin 23
vr0: Ethernet address: 00:e0:81:59:68:e4
ukphy0 at vr0 phy 1: OUI 0x0002c6, model 0x0032, rev. 10
ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
isa0 at viapcib0
com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, working fifo
com0: console
com1 at isa0 port 0x2f8-0x2ff irq 3: ns16550a, working fifo
pckbc0 at isa0 port 0x60-0x64
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0 mux 1
wskbd0: connecting to wsdisplay0
attimer0 at isa0 port 0x40-0x43
pcppi0 at isa0 port 0x61
midi0 at pcppi0: PC speaker
sysbeep0 at pcppi0
npx0 at isa0 port 0xf0-0xff
npx0: reported by CPUID; using exception 16
attimer0: attached to pcppi0
Initializing SSP: c27390a4 6212f8d8 e980c1a0 b41a9157 a4a14c45
63cbe0ef bf816db0 6f3407f0
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
cpu1: TSC skew=109030138706 drift=-8788792544
TSC not known safe on this CPU
timecounter: Timecounter "TSC" frequency 997225350 Hz quality -100
cpu1: running
uhub0 at usb0: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 2 ports with 2 removable, self powered
uhub1 at usb1: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1: 2 ports with 2 removable, self powered
uhub2 at usb2: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub2: 2 ports with 2 removable, self powered
uhub3 at usb3: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub3: 2 ports with 2 removable, self powered
viaide0 port 0: device present, speed: 1.5Gb/s
uhub4 at usb4: vendor 0x1106 EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub4: 8 ports with 8 removable, self powered
viaide0 port 1: device present, speed: 1.5Gb/s
wd0 at atabus0 drive 0
wd0: <HDS722516VLSA80>
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 153 GB, 319120 cyl, 16 head, 63 sec, 512 bytes/sect x 321672960 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
wd0(viaide0:0:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using DMA)
atapibus0 at atabus1: 2 targets
cd0 at atapibus0 drive 0: <HL-DT-ST DVDRAM GH22NS40, K5I98JK5513,
NL01> cdrom removable
cd0: 32-bit data port
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
cd0(viaide0:1:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using DMA)
crypto: assign driver 0, flags 2
crypto: driver 0 registers alg 1 flags 0 maxoplen 0
crypto: driver 0 registers alg 2 flags 0 maxoplen 0
crypto: driver 0 registers alg 3 flags 0 maxoplen 0
crypto: driver 0 registers alg 4 flags 0 maxoplen 0
crypto: driver 0 registers alg 5 flags 0 maxoplen 0
crypto: driver 0 registers alg 17 flags 0 maxoplen 0
crypto: driver 0 registers alg 6 flags 0 maxoplen 0
crypto: driver 0 registers alg 19 flags 0 maxoplen 0
crypto: driver 0 registers alg 7 flags 0 maxoplen 0
crypto: driver 0 registers alg 20 flags 0 maxoplen 0
crypto: driver 0 registers alg 15 flags 0 maxoplen 0
crypto: driver 0 registers alg 24 flags 0 maxoplen 0
crypto: driver 0 registers alg 25 flags 0 maxoplen 0
crypto: driver 0 registers alg 8 flags 0 maxoplen 0
crypto: driver 0 registers alg 21 flags 0 maxoplen 0
crypto: driver 0 registers alg 16 flags 0 maxoplen 0
crypto: driver 0 registers alg 9 flags 0 maxoplen 0
crypto: driver 0 registers alg 10 flags 0 maxoplen 0
crypto: driver 0 registers alg 13 flags 0 maxoplen 0
crypto: driver 0 registers alg 14 flags 0 maxoplen 0
crypto: driver 0 registers alg 11 flags 0 maxoplen 0
crypto: driver 0 registers alg 18 flags 0 maxoplen 0
crypto: driver 0 registers alg 23 flags 0 maxoplen 0
crypto: driver 0 registers alg 22 flags 0 maxoplen 0
raidattach: Asked for 8 units
Kernelized RAIDframe activated
Searching for RAID components...
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
uhidev0 at uhub0 port 1 configuration 1 interface 0
uhidev0: Logitech USB-PS/2 Optical Mouse, rev 2.00/20.00, addr 2, iclass 3/1
ums0 at uhidev0: 3 buttons and Z dir
wsmouse0 at ums0 mux 0
wsdisplay0: screen 1 added (80x25, vt100 emulation)
wsdisplay0: screen 2 added (80x25, vt100 emulation)
wsdisplay0: screen 3 added (80x25, vt100 emulation)
wsdisplay0: screen 4 added (80x25, vt100 emulation)
- Hide quoted text -
On Sun, Apr 3, 2011 at 3:25 AM, Andrius V <vezhlys@gmail.com> wrote:
> Hello,
>
> Unfortunately I didn't get any response to my last message so I
> debugged the system a little bit more... There is some small
> information that I missed previous times and can be helpful. I booted
> the system with debug messages (-vx) and got a bit more information.
> Firstly I received x86_ipi_init: ESR 00000040 message (it is from
> lapic.c x86_ipi_init function and target value equals 1). It means
> that IPI with illegal vector was received by Intel APIC specification.
> Maybe this is the point where the problem began? It happens before
> cpu_start_secondary and subsequently tsc_read_bp is executed (where
> I'm getting infinitive loop). Secondly, I also compared various values
> between correctly working system (dual core Athlon II X2) and VT-310DP
> in tsc_read_bp function during execution. It seems that these values
> were set correctly except that tsc_sync_cpu never becomes null on
> VT-310DP. I used quite recent NetBSD-current for tests so the problem
> remains in current version. Here is updated boot log with debug
> messages:
>
> Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
> 2006, 2007, 2008, 2009, 2010, 2011
> The NetBSD Foundation, Inc. All rights reserved.
> Copyright (c) 1982, 1986, 1989, 1991, 1993
> The Regents of the University of California. All rights reserved.
>
> NetBSD 5.99.48 (GENERIC) #0: Sun Mar 20 11:14:49 UTC 2011
> builds@b8.netbsd.org:/home/builds/ab/HEAD/i386/201103200600Z-obj/home/bC
> total memory = 1981 MB
> avail memory = 1935 MB
> Prep module path=ffs len=230310 pa=c4d000
> timecounter: Timecounters tick every 10.000 msec
> timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
> BIOS32 rev. 0 found at 0xfa2a0
> SMBIOS rev. 2.3 @ 0xf0000 (37 entries)
> VIA Technologies, Inc. CN400-8237 ( )
> mainbus0 (root)
> cpu0 at mainbus0 apid 0cpu0: calibrating local timer
> cpu0: apic clock running at 133 MHz
> timecounter: Timecounter "lapic" frequency 133032744 Hz quality -100
> : VIA Nehemiah, id 0x69a
> cpu0: PAT enabled
> cpu1 at mainbus0 apid 1x86_ipi_init: ESR 00000040
>
From: Andrius V <vezhlys@gmail.com>
To: Christos Zoulas <christos@zoulas.com>
Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org, gnats-bugs@netbsd.org
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Mon, 30 Apr 2012 02:43:10 +0300
Yes, I thought about the same thing but I didn't knew how to write it.
Patch almost worked but ECX8 bit needs to be written actually.
I added these lines to the end of your code before break:
msr =3D rdmsr(0x00001107);
wrmsr(0x00001107, msr | 0x00000001);
0x00001107 (Feature control register) and the first bit is ECX8 bit
(at least on Eden-N CPU).
That solved the problem and system booted with both CPU enabled.
On Mon, Apr 30, 2012 at 1:28 AM, Christos Zoulas <christos@zoulas.com> wrot=
e:
> On Apr 29, 11:27pm, vezhlys@gmail.com (Andrius V) wrote:
> -- Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VI=
A VT
>
> | I found the main problem for this bug. It is related to the patch made =
for
> | PR40213. Changes itself were not bad but for some reason (cpu_feature[0=
] &
> | CPUID_CX8) !=3D 0 (x86_patch function in patch.c) returns false for thi=
s
> | system (VIA Eden-N actually supports cmpxchg8b instruction). Because of
> | this it uses i486 version of atomic_cas_64 function (atomic.S) and this=
is
> | the place where it doesn't work. That code worked too until popf, pushf
> | were added and that change broke the support (it was made for "Fix the =
i486
> | atomic_cas_64() to not unconditionally enable interrupts.", if I am not
> | wrong), because of this atomic_swap_64 goes into infinitive loop too (l=
ook
> | at my earlier posts). The main question remains why pentium routine is =
not
> | used how to solve that? Currently I commented this if clause (so the
> | "patch" applied anyway) and system just booted fine with both CPUs. Any
> | thoughts and suggestions? Thanks.
>
> Can you try this patch? If it does not work, can you send me the cpuid ou=
tput
> for your processors (or add printf's and see why it does not)?
>
> christos
>
> Index: identcpu.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> RCS file: /cvsroot/src/sys/arch/x86/x86/identcpu.c,v
> retrieving revision 1.30
> diff -u -p -u -r1.30 identcpu.c
> --- identcpu.c =C2=A023 Feb 2012 14:45:55 -0000 =C2=A0 =C2=A0 =C2=A01.30
> +++ identcpu.c =C2=A029 Apr 2012 22:26:32 -0000
> @@ -380,13 +380,30 @@ static void
> =C2=A0cpu_probe_winchip(struct cpu_info *ci)
> =C2=A0{
>
> - =C2=A0 =C2=A0 =C2=A0 if (cpu_vendor !=3D CPUVENDOR_IDT ||
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUID2FAMILY(ci->ci_signature) !=3D =
5)
> + =C2=A0 =C2=A0 =C2=A0 if (cpu_vendor !=3D CPUVENDOR_IDT)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
>
> - =C2=A0 =C2=A0 =C2=A0 if (CPUID2MODEL(ci->ci_signature) =3D=3D 4) {
> + =C2=A0 =C2=A0 =C2=A0 switch (CPUID2FAMILY(ci->ci_signature)) {
> + =C2=A0 =C2=A0 =C2=A0 case 5:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* WinChip C6 */
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ci->ci_feat_val[0] &=
=3D ~CPUID_TSC;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (CPUID2MODEL(ci->ci=
_signature) =3D=3D 4)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 ci->ci_feat_val[0] &=3D ~CPUID_TSC;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> + =C2=A0 =C2=A0 =C2=A0 case 6:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* VIA Eden ESP
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Quoting from p=
age 3-4 of: "VIA Eden ESP Processor Datasheet"
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* http://www.via=
.com.tw/download/mainboards/6/14/Eden20v115.pdf
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* 1. The CMPXCHG=
8B instruction is provided and always enabled,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0h=
owever, it appears disabled in the corresponding CPUID
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0f=
unction bit 0 to avoid a bug in an early version of
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0W=
indows NT. However, this default can be changed via a
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0b=
it in the FCR MSR.
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ci->ci_feat_val[0] |=
=3D CPUID_CX8;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> =C2=A0}
>
From: "Christos Zoulas" <christos@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Sun, 29 Apr 2012 20:08:03 -0400
Module Name: src
Committed By: christos
Date: Mon Apr 30 00:08:03 UTC 2012
Modified Files:
src/sys/arch/x86/x86: identcpu.c
Log Message:
PR/41267: Andrius V: 5.0 RC4 does not detect second CPU in VIA. VIA Eden cpuid
lies about it's ability to do cmpxchg8b. Turn the feature on using the FCR MSR.
Needs pullup to both 5 and 6.
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: christos@zoulas.com (Christos Zoulas)
To: Andrius V <vezhlys@gmail.com>
Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org, gnats-bugs@netbsd.org
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA VT-310DP motherboard
Date: Sun, 29 Apr 2012 20:09:56 -0400
On Apr 30, 2:43am, vezhlys@gmail.com (Andrius V) wrote:
-- Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA VT
| Yes, I thought about the same thing but I didn't knew how to write it.
| Patch almost worked but ECX8 bit needs to be written actually.
|
| I added these lines to the end of your code before break:
|
| msr =3D rdmsr(0x00001107);
| wrmsr(0x00001107, msr | 0x00000001);
Thanks, I've committed a fix.
christos
From: Andrius V <vezhlys@gmail.com>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Mon, 30 Apr 2012 10:56:26 +0300
Didn't get sent to gnats-bugs. Very sorry for duplicate messages and
broken order.
------
I found the main problem for this bug. It is related to the patch made for
PR40213. Changes itself were not bad but for some reason (cpu_feature[0] &
CPUID_CX8) !=3D 0 (x86_patch function in patch.c) returns false for this
system (VIA Eden-N actually supports cmpxchg8b instruction). Because of th=
is
it uses i486 version of atomic_cas_64 function (atomic.S) and this is the
place where it doesn't work. That code worked too until popf, pushf were
added and that change broke the support (it was made for "Fix the i486
atomic_cas_64() to not unconditionally enable interrupts.", if I am not
wrong), because of this atomic_swap_64 goes into infinitive loop too (look
at my earlier posts). The main question remains why pentium routine is not
used how to solve that? Currently I commented this if clause (so the "patc=
h"
applied anyway) and system just booted fine with both CPUs. Any thoughts a=
nd
suggestions? Thanks.
On Mon, Apr 11, 2011 at 4:00 PM, Andrius V <vezhlys@gmail.com> wrote:
>
> The following reply was made to PR port-i386/41267; it has been noted by
> GNATS.
>
> From: Andrius V <vezhlys@gmail.com>
> To: gnats-bugs@netbsd.org
> Cc:
> Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
> =C2=A0VT-310DP motherboard
> Date: Mon, 11 Apr 2011 15:57:46 +0300
>
> =C2=A0Didn't sent to gnats-bugs (retry)
>
> =C2=A0Hello once again,
>
> =C2=A0I investigated the problem more and I found the exact place where
> =C2=A0something went wrong... I realized that tsc_read_bp function waits =
for
> =C2=A0results whose come from tsc_post_ap (functions from tsc.c). I print=
ed
> =C2=A0some text after every step in tsc_post_ap and found that it stopped
> =C2=A0printing before this line:
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Post result. =C2=A0Ensure the whole value g=
oes out atomically. */
> =C2=A0 =C2=A0 =C2=A0 =C2=A0(void)atomic_swap_64(&tsc_sync_val, tsc);
>
> =C2=A0I commented this line (I know that it is not a solution at all but =
I
> =C2=A0just wanted to be sure) and to my surprise the second cpu started..=
.
> =C2=A0Unfortunately one more problem appeared with via ide drivers
> =C2=A0(viaide0:0:0: lost interrupt), but I successfully booted NetBSD
> =C2=A0without acpi support (-2vx). I posted dmesg below. If somebody will
> =C2=A0help me to understand how atomic_swap_64 works on i386 architecture=
I
> =C2=A0might try to localize the problem even more...
>
> =C2=A0What is more I found that x86_ipi_init: ESR 00000040 problem comes
> =C2=A0after first i82489_writereg(LAPIC_ESR, 0); call (so it wasn't relat=
ed
> =C2=A0problem). If I add two function i82489_writereg(LAPIC_ESR, 0) calls
> =C2=A0one after another in x86_ipi_init then problem disappears and never
> =C2=A0reappears. If I comment this line then I am getting the same error =
in
> =C2=A0x86_ipi_startup function.
>
> =C2=A0dmesg represents this two changes I described (commented
> =C2=A0atomic_swap_64 line and added second i82489_writereg(LAPIC_ESR, 0);
> =C2=A0call in x86_ipi_init), -2vx arguments used:
>
> =C2=A0rbus: rbus_min_start set to 0x80000000
> =C2=A0Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,=
2005,
> =C2=A0 =C2=A02006, 2007, 2008, 2009, 2010, 2011
> =C2=A0 =C2=A0The NetBSD Foundation, Inc. =C2=A0All rights reserved.
> =C2=A0Copyright (c) 1982, 1986, 1989, 1991, 1993
> =C2=A0 =C2=A0The Regents of the University of California. =C2=A0All right=
s reserved.
>
> =C2=A0NetBSD 5.99.48 (VT-3102) #58: Mon Apr 11 04:50:22 EEST 2011
>
> =C2=A0andrius@agraphic-vt310dp.VIDANDRIUS:/usr/src/sys/arch/i386/compile/=
VT-3102
> =C2=A0total memory =3D 1981 MB
> =C2=A0avail memory =3D 1935 MB
> =C2=A0Prep module path=3Dffs len=3D230310 pa=3Dc4d000
> =C2=A0timecounter: Timecounters tick every 10.000 msec
> =C2=A0timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
> =C2=A0BIOS32 rev. 0 found at 0xfa2a0
> =C2=A0SMBIOS rev. 2.3 @ 0xf0000 (37 entries)
> =C2=A0VIA Technologies, Inc. CN400-8237 ( )
> =C2=A0mainbus0 (root)
> =C2=A0mainbus0: Intel MP Specification (Version 1.4) (OEM00000 PROD000000=
00)
> =C2=A0cpu0 at mainbus0 apid 0cpu0: calibrating local timer
> =C2=A0cpu0: apic clock running at 133 MHz
> =C2=A0timecounter: Timecounter "lapic" frequency 133032544 Hz quality -10=
0
> =C2=A0: VIA Nehemiah, id 0x69a
> =C2=A0cpu0: PAT enabled
> =C2=A0cpu1 at mainbus0 apid 1: VIA Nehemiah, id 0x69a
> =C2=A0cpu1: PAT enabled
> =C2=A0mpbios: bus 0 is type PCI
> =C2=A0mpbios: bus 1 is type PCI
> =C2=A0mpbios: bus 2 is type ISA
> =C2=A0ioapic0 at mainbus0 apid 2: pa 0xfec00000, version 3, 24 pins
> =C2=A0ioapic0: misconfigured as apic 0
> =C2=A0ioapic0: remapped to apic 2
> =C2=A0pci0 at mainbus0 bus 0: configuration mode 1
> =C2=A0pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
> =C2=A0pchb0 at pci0 dev 0 function 0: vendor 0x1106 product 0x0259 (rev. =
0x00)
> =C2=A0agp0 at pchb0 (v3): aperture at 0xe8000000, size 0x8000000
> =C2=A0pchb1 at pci0 dev 0 function 1: vendor 0x1106 product 0x1259 (rev. =
0x00)
> =C2=A0pchb2 at pci0 dev 0 function 2: vendor 0x1106 product 0x2259 (rev. =
0x00)
> =C2=A0pchb3 at pci0 dev 0 function 3: vendor 0x1106 product 0x3259 (rev. =
0x00)
> =C2=A0pchb4 at pci0 dev 0 function 4: vendor 0x1106 product 0x4259 (rev. =
0x00)
> =C2=A0pchb5 at pci0 dev 0 function 7: vendor 0x1106 product 0x7259 (rev. =
0x00)
> =C2=A0ppb0 at pci0 dev 1 function 0: vendor 0x1106 product 0xb198 (rev. 0=
x00)
> =C2=A0pci1 at ppb0 bus 1
> =C2=A0pci1: i/o space, memory space enabled
> =C2=A0vga1 at pci1 dev 0 function 0: vendor 0x1106 product 0x3118 (rev. 0=
x02)
> =C2=A0wsdisplay0 at vga1 kbdmux 1
> =C2=A0wsmux1: connecting to wsdisplay0
> =C2=A0viadrm0 at vga1pci_mem_find: void region
> =C2=A0pci_mem_find: void region
> =C2=A0pci_mem_find: void region
> =C2=A0pci_mem_find: void region
> =C2=A0: VIA CN400 / PM8X0
> =C2=A0viadrm0: AGP at 0xe8000000 128MB
> =C2=A0viadrm0: Initialized via 2.11.1 20070202
> =C2=A0fxp0 at pci0 dev 9 function 0: i82551 Ethernet, rev 16
> =C2=A0fxp0: interrupting at ioapic0 pin 17
> =C2=A0fxp0: Ethernet address 00:e0:81:59:68:e5
> =C2=A0inphy0 at fxp0 phy 1: i82555 10/100 media interface, rev. 4
> =C2=A0inphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
> =C2=A0vge0 at pci0 dev 10 function 0: VIA VT612X Gigabit Ethernet (rev. 0=
x11)
> =C2=A0vge0: interrupting at ioapic0 pin 18
> =C2=A0vge0: Ethernet address: 00:e0:81:59:68:e3
> =C2=A0ciphy0 at vge0 phy 1: Cicada CS8201 10/100/1000TX PHY, rev. 2
> =C2=A0ciphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
> =C2=A01000baseT-FDX, auto
> =C2=A0pci_mem_find: expected type mem, found i/o
> =C2=A0viaide0 at pci0 dev 15 function 0: VIA Technologies VT8237 SATA
> =C2=A0Controller (rev. 0x80)
> =C2=A0viaide0: bus-master DMA support present
> =C2=A0viaide0: primary channel wired to native-PCI mode
> =C2=A0viaide0: using ioapic0 pin 20 for native-PCI interrupt
> =C2=A0atabus0 at viaide0 channel 0
> =C2=A0viaide0: secondary channel wired to native-PCI mode
> =C2=A0atabus1 at viaide0 channel 1
> =C2=A0uhci0 at pci0 dev 16 function 0: vendor 0x1106 product 0x3038 (rev.=
0x81)
> =C2=A0uhci0: interrupting at ioapic0 pin 21
> =C2=A0usb0 at uhci0: USB revision 1.0
> =C2=A0usb0: WARNING: power management not supported
> =C2=A0uhci1 at pci0 dev 16 function 1: vendor 0x1106 product 0x3038 (rev.=
0x81)
> =C2=A0uhci1: interrupting at ioapic0 pin 21
> =C2=A0usb1 at uhci1: USB revision 1.0
> =C2=A0usb1: WARNING: power management not supported
> =C2=A0uhci2 at pci0 dev 16 function 2: vendor 0x1106 product 0x3038 (rev.=
0x81)
> =C2=A0uhci2: interrupting at ioapic0 pin 21
> =C2=A0usb2 at uhci2: USB revision 1.0
> =C2=A0usb2: WARNING: power management not supported
> =C2=A0uhci3 at pci0 dev 16 function 3: vendor 0x1106 product 0x3038 (rev.=
0x81)
> =C2=A0uhci3: interrupting at ioapic0 pin 21
> =C2=A0usb3 at uhci3: USB revision 1.0
> =C2=A0usb3: WARNING: power management not supported
> =C2=A0ehci0 at pci0 dev 16 function 4: vendor 0x1106 product 0x3104 (rev.=
0x86)
> =C2=A0ehci0: interrupting at ioapic0 pin 21
> =C2=A0ehci0: dropped intr workaround enabled
> =C2=A0ehci0: BIOS refuses to give up ownership, using force
> =C2=A0ehci0: EHCI version 1.0
> =C2=A0ehci0: companion controllers, 2 ports each: uhci0 uhci1 uhci2 uhci3
> =C2=A0usb4 at ehci0: USB revision 2.0
> =C2=A0usb4: WARNING: power management not supported
> =C2=A0viapcib0 at pci0 dev 17 function 0: vendor 0x1106 product 0x3227 (r=
ev.
> 0x00)
> =C2=A0viapcib0: SMBus found at 0x500 (revision 0x0)
> =C2=A0iic0 at viapcib0: I2C bus
> =C2=A0auvia0 at pci0 dev 17 function 5: VIA Technologies VT8237 AC'97 Aud=
io
> (rev 0x60)
> =C2=A0auvia0: interrupting at ioapic0 pin 22
> =C2=A0auvia0: ac97: VIA Technologies VT1616i codec; headphone, 18 bit DAC=
,
> =C2=A018 bit ADC, KS Waves 3D
> =C2=A0auvia0: ac97: ext id 0x1c1<LDAC,SDAC,CDAC,VRA>
> =C2=A0audio0 at auvia0: full duplex, playback, capture, mmap, independent
> =C2=A0vr0 at pci0 dev 18 function 0: vendor 0x1106 product 0x3065 (rev. 0=
x78)
> =C2=A0vr0: interrupting at ioapic0 pin 23
> =C2=A0vr0: Ethernet address: 00:e0:81:59:68:e4
> =C2=A0ukphy0 at vr0 phy 1: OUI 0x0002c6, model 0x0032, rev. 10
> =C2=A0ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
> =C2=A0isa0 at viapcib0
> =C2=A0com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, working fifo
> =C2=A0com0: console
> =C2=A0com1 at isa0 port 0x2f8-0x2ff irq 3: ns16550a, working fifo
> =C2=A0pckbc0 at isa0 port 0x60-0x64
> =C2=A0pckbd0 at pckbc0 (kbd slot)
> =C2=A0pckbc0: using irq 1 for kbd slot
> =C2=A0wskbd0 at pckbd0 mux 1
> =C2=A0wskbd0: connecting to wsdisplay0
> =C2=A0attimer0 at isa0 port 0x40-0x43
> =C2=A0pcppi0 at isa0 port 0x61
> =C2=A0midi0 at pcppi0: PC speaker
> =C2=A0sysbeep0 at pcppi0
> =C2=A0npx0 at isa0 port 0xf0-0xff
> =C2=A0npx0: reported by CPUID; using exception 16
> =C2=A0attimer0: attached to pcppi0
> =C2=A0Initializing SSP: c27390a4 6212f8d8 e980c1a0 b41a9157 a4a14c45
> =C2=A063cbe0ef bf816db0 6f3407f0
> =C2=A0timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality =
0
> =C2=A0cpu1: TSC skew=3D109030138706 drift=3D-8788792544
> =C2=A0TSC not known safe on this CPU
> =C2=A0timecounter: Timecounter "TSC" frequency 997225350 Hz quality -100
> =C2=A0cpu1: running
> =C2=A0uhub0 at usb0: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.0=
0,
> addr 1
> =C2=A0uhub0: 2 ports with 2 removable, self powered
> =C2=A0uhub1 at usb1: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.0=
0,
> addr 1
> =C2=A0uhub1: 2 ports with 2 removable, self powered
> =C2=A0uhub2 at usb2: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.0=
0,
> addr 1
> =C2=A0uhub2: 2 ports with 2 removable, self powered
> =C2=A0uhub3 at usb3: vendor 0x1106 UHCI root hub, class 9/0, rev 1.00/1.0=
0,
> addr 1
> =C2=A0uhub3: 2 ports with 2 removable, self powered
> =C2=A0viaide0 port 0: device present, speed: 1.5Gb/s
> =C2=A0uhub4 at usb4: vendor 0x1106 EHCI root hub, class 9/0, rev 2.00/1.0=
0,
> addr 1
> =C2=A0uhub4: 8 ports with 8 removable, self powered
> =C2=A0viaide0 port 1: device present, speed: 1.5Gb/s
> =C2=A0wd0 at atabus0 drive 0
> =C2=A0wd0: <HDS722516VLSA80>
> =C2=A0wd0: drive supports 16-sector PIO transfers, LBA48 addressing
> =C2=A0wd0: 153 GB, 319120 cyl, 16 head, 63 sec, 512 bytes/sect x 32167296=
0
> sectors
> =C2=A0wd0: 32-bit data port
> =C2=A0wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra=
/100)
> =C2=A0wd0(viaide0:0:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (u=
sing
> DMA)
> =C2=A0atapibus0 at atabus1: 2 targets
> =C2=A0cd0 at atapibus0 drive 0: <HL-DT-ST DVDRAM GH22NS40, K5I98JK5513,
> =C2=A0NL01> cdrom removable
> =C2=A0cd0: 32-bit data port
> =C2=A0cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra=
/100)
> =C2=A0cd0(viaide0:1:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (u=
sing
> DMA)
> =C2=A0crypto: assign driver 0, flags 2
> =C2=A0crypto: driver 0 registers alg 1 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 2 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 3 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 4 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 5 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 17 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 6 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 19 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 7 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 20 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 15 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 24 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 25 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 8 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 21 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 16 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 9 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 10 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 13 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 14 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 11 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 18 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 23 flags 0 maxoplen 0
> =C2=A0crypto: driver 0 registers alg 22 flags 0 maxoplen 0
> =C2=A0raidattach: Asked for 8 units
> =C2=A0Kernelized RAIDframe activated
> =C2=A0Searching for RAID components...
> =C2=A0boot device: wd0
> =C2=A0root on wd0a dumps on wd0b
> =C2=A0root file system type: ffs
> =C2=A0uhidev0 at uhub0 port 1 configuration 1 interface 0
> =C2=A0uhidev0: Logitech USB-PS/2 Optical Mouse, rev 2.00/20.00, addr 2, i=
class
> 3/1
> =C2=A0ums0 at uhidev0: 3 buttons and Z dir
> =C2=A0wsmouse0 at ums0 mux 0
> =C2=A0wsdisplay0: screen 1 added (80x25, vt100 emulation)
> =C2=A0wsdisplay0: screen 2 added (80x25, vt100 emulation)
> =C2=A0wsdisplay0: screen 3 added (80x25, vt100 emulation)
> =C2=A0wsdisplay0: screen 4 added (80x25, vt100 emulation)
> =C2=A0- Hide quoted text -
>
>
> =C2=A0On Sun, Apr 3, 2011 at 3:25 AM, Andrius V <vezhlys@gmail.com> wrote=
:
> =C2=A0> Hello,
> =C2=A0>
> =C2=A0> Unfortunately I didn't get any response to my last message so I
> =C2=A0> debugged the system a little bit more... There is some small
> =C2=A0> information that I missed previous times and can be helpful. I bo=
oted
> =C2=A0> the system with debug messages (-vx) and got a bit more informati=
on.
> =C2=A0> Firstly I received x86_ipi_init: ESR 00000040 message (it is from
> =C2=A0> lapic.c x86_ipi_init function and target value equals 1). It mean=
s
> =C2=A0> that IPI with illegal vector was received by Intel APIC specifica=
tion.
> =C2=A0> Maybe this is the point where the problem began? It happens befor=
e
> =C2=A0> cpu_start_secondary and subsequently tsc_read_bp is executed (whe=
re
> =C2=A0> I'm getting infinitive loop). Secondly, I also compared various v=
alues
> =C2=A0> between correctly working system (dual core Athlon II X2) and VT-=
310DP
> =C2=A0> in tsc_read_bp function during execution. It seems that these val=
ues
> =C2=A0> were set correctly except that tsc_sync_cpu never becomes null on
> =C2=A0> VT-310DP. I used quite recent NetBSD-current for tests so the pro=
blem
> =C2=A0> remains in current version. Here is updated boot log with debug
> =C2=A0> messages:
> =C2=A0>
> =C2=A0> Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 200=
4,
> 2005,
> =C2=A0> =C2=A0 =C2=A02006, 2007, 2008, 2009, 2010, 2011
> =C2=A0> =C2=A0 =C2=A0The NetBSD Foundation, Inc. =C2=A0All rights reserve=
d.
> =C2=A0> Copyright (c) 1982, 1986, 1989, 1991, 1993
> =C2=A0> =C2=A0 =C2=A0The Regents of the University of California. =C2=A0A=
ll rights reserved.
> =C2=A0>
> =C2=A0> NetBSD 5.99.48 (GENERIC) #0: Sun Mar 20 11:14:49 UTC 2011
> =C2=A0>
> =C2=A0builds@b8.netbsd.org:/home/builds/ab/HEAD/i386/201103200600Z-obj/ho=
me/bC
> =C2=A0> total memory =3D 1981 MB
> =C2=A0> avail memory =3D 1935 MB
> =C2=A0> Prep module path=3Dffs len=3D230310 pa=3Dc4d000
> =C2=A0> timecounter: Timecounters tick every 10.000 msec
> =C2=A0> timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
> =C2=A0> BIOS32 rev. 0 found at 0xfa2a0
> =C2=A0> SMBIOS rev. 2.3 @ 0xf0000 (37 entries)
> =C2=A0> VIA Technologies, Inc. CN400-8237 ( )
> =C2=A0> mainbus0 (root)
> =C2=A0> cpu0 at mainbus0 apid 0cpu0: calibrating local timer
> =C2=A0> cpu0: apic clock running at 133 MHz
> =C2=A0> timecounter: Timecounter "lapic" frequency 133032744 Hz quality -=
100
> =C2=A0> : VIA Nehemiah, id 0x69a
> =C2=A0> cpu0: PAT enabled
> =C2=A0> cpu1 at mainbus0 apid 1x86_ipi_init: ESR 00000040
> =C2=A0>
>
From: Andrius V <vezhlys@gmail.com>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Mon, 30 Apr 2012 11:00:49 +0300
Wasn't sent to gnats-bugs. Very sorry for duplicate messages and broken ord=
er.
------
On Mon, Apr 30, 2012 at 1:28 AM, Christos Zoulas <christos@zoulas.com> wrot=
e:
On Apr 29, 11:27pm, vezhlys@gmail.com (Andrius V) wrote:
-- Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA=
VT
| I found the main problem for this bug. It is related to the patch made f=
or
| PR40213. Changes itself were not bad but for some reason (cpu_feature[0]=
&
| CPUID_CX8) !=3D 0 (x86_patch function in patch.c) returns false for this
| system (VIA Eden-N actually supports cmpxchg8b instruction). Because of
| this it uses i486 version of atomic_cas_64 function (atomic.S) and this =
is
| the place where it doesn't work. That code worked too until popf, pushf
| were added and that change broke the support (it was made for "Fix the i=
486
| atomic_cas_64() to not unconditionally enable interrupts.", if I am not
| wrong), because of this atomic_swap_64 goes into infinitive loop too (lo=
ok
| at my earlier posts). The main question remains why pentium routine is n=
ot
| used how to solve that? Currently I commented this if clause (so the
| "patch" applied anyway) and system just booted fine with both CPUs. Any
| thoughts and suggestions? Thanks.
Can you try this patch? If it does not work, can you send me the cpuid out=
put
for your processors (or add printf's and see why it does not)?
christos
Index: identcpu.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/arch/x86/x86/identcpu.c,v
retrieving revision 1.30
diff -u -p -u -r1.30 identcpu.c
--- identcpu.c =C2=A023 Feb 2012 14:45:55 -0000 =C2=A0 =C2=A0 =C2=A01.30
+++ identcpu.c =C2=A029 Apr 2012 22:26:32 -0000
@@ -380,13 +380,30 @@ static void
=C2=A0cpu_probe_winchip(struct cpu_info *ci)
=C2=A0{
- =C2=A0 =C2=A0 =C2=A0 if (cpu_vendor !=3D CPUVENDOR_IDT ||
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUID2FAMILY(ci->ci_signature) !=3D 5=
)
+ =C2=A0 =C2=A0 =C2=A0 if (cpu_vendor !=3D CPUVENDOR_IDT)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
- =C2=A0 =C2=A0 =C2=A0 if (CPUID2MODEL(ci->ci_signature) =3D=3D 4) {
+ =C2=A0 =C2=A0 =C2=A0 switch (CPUID2FAMILY(ci->ci_signature)) {
+ =C2=A0 =C2=A0 =C2=A0 case 5:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* WinChip C6 */
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ci->ci_feat_val[0] &=3D=
~CPUID_TSC;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (CPUID2MODEL(ci->ci_=
signature) =3D=3D 4)
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 ci->ci_feat_val[0] &=3D ~CPUID_TSC;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+ =C2=A0 =C2=A0 =C2=A0 case 6:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* VIA Eden ESP
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Quoting from pa=
ge 3-4 of: "VIA Eden ESP Processor Datasheet"
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*
http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* 1. The CMPXCHG8=
B instruction is provided and always enabled,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0ho=
wever, it appears disabled in the corresponding CPUID
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0fu=
nction bit 0 to avoid a bug in an early version of
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0Wi=
ndows NT. However, this default can be changed via a
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* =C2=A0 =C2=A0bi=
t in the FCR MSR.
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ci->ci_feat_val[0] |=3D=
CPUID_CX8;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
=C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0}
From: Andrius V <vezhlys@gmail.com>
To: Christos Zoulas <christos@zoulas.com>
Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org, gnats-bugs@netbsd.org
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA
VT-310DP motherboard
Date: Mon, 30 Apr 2012 12:12:30 +0300
On Mon, Apr 30, 2012 at 3:09 AM, Christos Zoulas <christos@zoulas.com> wrot=
e:
> On Apr 30, =C2=A02:43am, vezhlys@gmail.com (Andrius V) wrote:
> -- Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VI=
A VT
>
> | Yes, I thought about the same thing but I didn't knew how to write it.
> | Patch almost worked but ECX8 bit needs to be written actually.
> |
> | I added these lines to the end of your code before break:
> |
> | msr =3D3D rdmsr(0x00001107);
> | wrmsr(0x00001107, msr | 0x00000001);
>
> Thanks, I've committed a fix.
>
> christos
Thank you, I am happy that this annoying problem was finally fixed and
I was helpful.
Regards,
Andrius V
From: christos@zoulas.com (Christos Zoulas)
To: Andrius V <vezhlys@gmail.com>
Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org, gnats-bugs@netbsd.org
Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA VT-310DP motherboard
Date: Mon, 30 Apr 2012 08:59:58 -0400
On Apr 30, 12:12pm, vezhlys@gmail.com (Andrius V) wrote:
-- Subject: Re: port-i386/41267: 5.0 RC4 does not detect second CPU in VIA VT
| > | msr =3D3D rdmsr(0x00001107);
| > | wrmsr(0x00001107, msr | 0x00000001);
| >
| > Thanks, I've committed a fix.
| >
| > christos
|
| Thank you, I am happy that this annoying problem was finally fixed and
| I was helpful.
You were extremely helpful! You pointed out exactly what the bug was. Many thanks!
christos
From: "Jeff Rizzo" <riz@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/41267 CVS commit: [netbsd-6] src/sys/arch/x86
Date: Mon, 7 May 2012 16:37:19 +0000
Module Name: src
Committed By: riz
Date: Mon May 7 16:37:19 UTC 2012
Modified Files:
src/sys/arch/x86/include [netbsd-6]: specialreg.h
src/sys/arch/x86/x86 [netbsd-6]: identcpu.c
Log Message:
Pull up following revision(s) (requested by christos in ticket #220):
sys/arch/x86/x86/identcpu.c: revision 1.31
sys/arch/x86/include/specialreg.h: revision 1.58
PR/41267: Andrius V: 5.0 RC4 does not detect second CPU in VIA. VIA Eden cpuid
lies about it's ability to do cmpxchg8b. Turn the feature on using the FCR MSR.
Needs pullup to both 5 and 6.
Add VIA Eden FCR MSR.
To generate a diff of this commit:
cvs rdiff -u -r1.55.2.2 -r1.55.2.3 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.29.2.1 -r1.29.2.2 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: David Holland <dholland-bugs@netbsd.org>
To: gnats-bugs@NetBSD.org
Cc: Christos Zoulas <christos@netbsd.org>
Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Sat, 25 Aug 2012 18:54:55 +0000
On Mon, Apr 30, 2012 at 12:10:06AM +0000, Christos Zoulas wrote:
> From: "Christos Zoulas" <christos@netbsd.org>
> To: gnats-bugs@gnats.NetBSD.org
> Cc:
> Subject: PR/41267 CVS commit: src/sys/arch/x86/x86
> Date: Sun, 29 Apr 2012 20:08:03 -0400
>
> Module Name: src
> Committed By: christos
> Date: Mon Apr 30 00:08:03 UTC 2012
>
> Modified Files:
> src/sys/arch/x86/x86: identcpu.c
>
> Log Message:
> PR/41267: Andrius V: 5.0 RC4 does not detect second CPU in VIA. VIA Eden cpuid
> lies about it's ability to do cmpxchg8b. Turn the feature on using the FCR MSR.
> Needs pullup to both 5 and 6.
>
>
> To generate a diff of this commit:
> cvs rdiff -u -r1.30 -r1.31 src/sys/arch/x86/x86/identcpu.c
>
> Please note that diffs are not public domain; they are subject to the
> copyright notices on the relevant files.
I don't see a -5 pullup for this; did I miss it or does it still need
to be filed?
--
David A. Holland
dholland@netbsd.org
From: christos@zoulas.com (Christos Zoulas)
To: David Holland <dholland-bugs@netbsd.org>, gnats-bugs@NetBSD.org
Cc:
Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Sat, 25 Aug 2012 15:25:54 -0400
On Aug 25, 6:54pm, dholland-bugs@netbsd.org (David Holland) wrote:
-- Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
| I don't see a -5 pullup for this; did I miss it or does it still need
| to be filed?
Yes, I believe so.
christos
From: Andrius V <vezhlys@gmail.com>
To: gnats-bugs@netbsd.org
Cc: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org
Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Thu, 6 Sep 2012 01:32:15 +0300
You didn't miss it. Fix was applied to netbsd-6 branch only.
Regards,
Andrius V
On Sat, Aug 25, 2012 at 10:30 PM, Christos Zoulas <christos@zoulas.com> wrote:
> The following reply was made to PR port-i386/41267; it has been noted by GNATS.
>
> From: christos@zoulas.com (Christos Zoulas)
> To: David Holland <dholland-bugs@netbsd.org>, gnats-bugs@NetBSD.org
> Cc:
> Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
> Date: Sat, 25 Aug 2012 15:25:54 -0400
>
> On Aug 25, 6:54pm, dholland-bugs@netbsd.org (David Holland) wrote:
> -- Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
>
> | I don't see a -5 pullup for this; did I miss it or does it still need
> | to be filed?
>
> Yes, I believe so.
>
> christos
>
From: David Holland <dholland-bugs@netbsd.org>
To: gnats-bugs@netbsd.org
Cc:
Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Mon, 19 Nov 2012 05:08:09 +0000
(not sent to gnats-bugs)
------
From: Andrius V <vezhlys@gmail.com>
To: port-i386-maintainer@netbsd.org, gnats-admin@netbsd.org,
netbsd-bugs@netbsd.org, Andrius V <vezhlys@gmail.com>
Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Mon, 19 Nov 2012 00:33:10 +0200
Dumb question will it be pulled up to netbsd-5? NetBSD 5.2 RC1 still
doesn't have these changes.
From: "Jeff Rizzo" <riz@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/41267 CVS commit: [netbsd-5] src/sys/arch/x86/x86
Date: Mon, 26 Nov 2012 19:44:27 +0000
Module Name: src
Committed By: riz
Date: Mon Nov 26 19:44:27 UTC 2012
Modified Files:
src/sys/arch/x86/x86 [netbsd-5]: identcpu.c
Log Message:
Pull up following revision(s) (requested by christos in ticket #1819):
sys/arch/x86/x86/identcpu.c: revision 1.31
PR/41267: Andrius V: 5.0 RC4 does not detect second CPU in VIA. VIA Eden cpuid
lies about it's ability to do cmpxchg8b. Turn the feature on using the FCR MSR.
Needs pullup to both 5 and 6.
To generate a diff of this commit:
cvs rdiff -u -r1.10.4.6 -r1.10.4.7 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
From: "Greg A. Woods" <woods@planix.ca>
To: NetBSD GNATS <gnats-bugs@NetBSD.org>
Cc: port-i386-maintainer@netbsd.org, Jeff Rizzo <riz@netbsd.org>
Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Tue, 27 Nov 2012 20:13:38 -0800
--pgp-sign-Multipart_Tue_Nov_27_20:13:38_2012-1
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
I don't know if this has showed up in anyone else's build yet, but the
following change also must be pulled up to netbsd-5 in order to fix the
kernel build errors below:
RCS file: /cvs/master/m-NetBSD/main/src/sys/arch/x86/include/specialreg.h,v
Working file: specialreg.h
head: 1.60
----------------------------
revision 1.58
date: 2012/04/30 00:04:31; author: christos; state: Exp; lines: +6 -1
Add VIA Eden FCR MSR.
----------------------------
m-NetBSD-5/sys/arch/x86/x86/identcpu.c: In function 'cpu_probe_winchip':
m-NetBSD-5/sys/arch/x86/x86/identcpu.c:413: error: 'MSR_VIA_FCR' undeclared=
(first use in this function)
m-NetBSD-5/sys/arch/x86/x86/identcpu.c:413: error: (Each undeclared identif=
ier is reported only once
m-NetBSD-5/sys/arch/x86/x86/identcpu.c:413: error: for each function it app=
ears in.)
Any time anyone changes something like this, especially for a specific
kernel on a release branch, it would be a very good idea to fire off a
quick compile for at least the ALL or GENERIC config of that kernel
_before_ running "cvs commit"!
It seems the last "daily" snapshot build for the netbsd-5 branch was
from a few days ago, back 2012-11-24, so it's not very useful for
detecting these kinds of errors on release branches in a timely fashion.
--=20
Greg A. Woods
+1 250 762-7675 <gwoods@acm.org> RoboHack <woods@robohack.ca>
Planix, Inc. <woods@planix.com> Secrets of the Weird <woods@weird.com>
--pgp-sign-Multipart_Tue_Nov_27_20:13:38_2012-1
Content-Type: application/pgp-signature
Content-Transfer-Encoding: 7bit
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Version: GnuPG v1.4.10 (NetBSD)
iEYEABECAAYFAlC1j3IACgkQZn1xt3i/9H/uewCeLxoVdVUwT3P5+XLlm55EAuh9
3+MAn3mpqWCXHtn98f98xdcX+jhxLOf5
=p1+v
-----END PGP SIGNATURE-----
--pgp-sign-Multipart_Tue_Nov_27_20:13:38_2012-1--
From: Jeff Rizzo <riz@NetBSD.org>
To: "Greg A. Woods" <woods@weird.com>
Cc: "Greg A. Woods" <woods@planix.ca>,
NetBSD GNATS <gnats-bugs@NetBSD.org>,
port-i386-maintainer@netbsd.org
Subject: Re: PR/41267 CVS commit: src/sys/arch/x86/x86
Date: Tue, 27 Nov 2012 22:36:13 -0800
On 11/27/12 8:13 PM, Greg A. Woods wrote:
> I don't know if this has showed up in anyone else's build yet, but the
> following change also must be pulled up to netbsd-5 in order to fix the
> kernel build errors below:
already fixed, thanks.
State-Changed-From-To: open->closed
State-Changed-By: dholland@NetBSD.org
State-Changed-When: Fri, 04 Jan 2013 10:10:26 +0000
State-Changed-Why:
Pulled up to both -5 and -6.
>Unformatted:
(Contact us)
$NetBSD: query-full-pr,v 1.39 2013/11/01 18:47:49 spz Exp $
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