NetBSD Problem Report #41290

From paul@whooppee.com  Mon Apr 27 16:24:17 2009
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Date: Mon, 27 Apr 2009 09:24:16 -0700 (PDT)
From: paul@whooppee.com
Reply-To: paul@whooppee.com
To: gnats-bugs@gnats.NetBSD.org
Subject: cpuctl needs to wrap Intel features2 line
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>Number:         41290
>Category:       bin
>Synopsis:       cpuctl needs to wrap Intel features2 line
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    pgoyette
>State:          closed
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Mon Apr 27 16:25:00 +0000 2009
>Closed-Date:    Sun May 17 11:34:01 +0000 2009
>Last-Modified:  Mon May 18 19:45:01 +0000 2009
>Originator:     Paul Goyette
>Release:        NetBSD 5.99.11
>Organization:
-------------------------------------------------------------------------
|   Paul Goyette   | PGP DSS Key fingerprint: |  E-mail addresses:      |
| Customer Service | FA29 0E3B 35AF E8AE 6651 |  paul at whooppee.com   |
| Network Engineer | 0786 F758 55DE 53BA 7731 | pgoyette at juniper.net |
| Kernel Developer |                          | pgoyette at netbsd.org  |
-------------------------------------------------------------------------
>Environment:


System: NetBSD quicky.whooppee.com 5.99.11 NetBSD 5.99.11 (QUICKY (ASUS M2N32 WS) 2009-04-26 02:32:52) #0: Sat Apr 25 21:32:40 PDT 2009 paul@speedy.whooppee.com:/build/netbsd-local/obj/amd64/sys/arch/amd64/compile/QUICKY amd64
Architecture: x86_64
Machine: amd64
>Description:
Intel features2 line can have a lot of bits set.  It should be broken
up into multiple lines, as has been done with other features lines.

>How-To-Repeat:
bolt:paul {102} cpuctl identify 0
Cannot bind to target CPU.  Output may not accurately describe the target.
Run as root to allow binding.

cpu0: Intel Pentium III Xeon (Cascades) (686-class), 2672.81 MHz, id 0x106a5
cpu0: features 0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features 0xbfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>
cpu0: features 0xbfebfbff<FXSR,SSE,SSE2,SS,HTT,TM,SBF>
cpu0: features2 0x98e3bd<SSE3,DTES64,MONITOR,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE41,SSE42,POPCNT>
cpu0: features3 0x28100800<SYSCALL/SYSRET,XD,EM64T>
cpu0: "Intel(R) Core(TM) i7 CPU         920  @ 2.67GHz"
cpu0: D-cache 32KB 64B/line 8-way
cpu0: DTLB 64 4KB entries 4-way
cpu0: Initial APIC ID 3
cpu0: Cluster/Package ID 0
cpu0: Core ID 1
cpu0: SMT ID 1
cpu0: family 06 model 0a extfamily 00 extmodel 01


>Fix:


>Release-Note:

>Audit-Trail:

Responsible-Changed-From-To: bin-bug-people->pgoyette
Responsible-Changed-By: pgoyette@NetBSD.org
Responsible-Changed-When: Mon, 27 Apr 2009 20:19:21 +0000
Responsible-Changed-Why:
I'm working on it.


State-Changed-From-To: open->analyzed
State-Changed-By: pgoyette@NetBSD.org
State-Changed-When: Tue, 28 Apr 2009 23:30:11 +0000
State-Changed-Why:
I have a fix, pending comment/review on tech-userlevel@


From: Paul Goyette <pgoyette@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/41290 CVS commit: src
Date: Wed, 13 May 2009 22:25:51 +0000

 Module Name:	src
 Committed By:	pgoyette
 Date:		Wed May 13 22:25:51 UTC 2009

 Modified Files:
 	src/sys/arch/x86/include: cacheinfo.h specialreg.h
 	src/usr.sbin/cpuctl/arch: i386.c

 Log Message:
 1. Extend CPU probe of Intel processors to handle extended-models.  This
    allows us to properly identify new Intel 45nm processors, Core i7,
    Atom, and the 45nm Xeon MP.

 2. Properly decode several new Intel cache descriptors, as listed in the
    most recent (March 2009) edition of Intel's Application Note 485.

 3. Convert decode of the various features masks to use the newly added
    snprintb_m(3) routine.

 Addresses my PR bin/41289
 Addresses my PR bin/41290


 To generate a diff of this commit:
 cvs rdiff -u -r1.10 -r1.11 src/sys/arch/x86/include/cacheinfo.h
 cvs rdiff -u -r1.33 -r1.34 src/sys/arch/x86/include/specialreg.h
 cvs rdiff -u -r1.17 -r1.18 src/usr.sbin/cpuctl/arch/i386.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

State-Changed-From-To: analyzed->closed
State-Changed-By: pgoyette@NetBSD.org
State-Changed-When: Sun, 17 May 2009 11:34:01 +0000
State-Changed-Why:
Fixed.


From: Manuel Bouyer <bouyer@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/41290 CVS commit: [netbsd-5] src
Date: Mon, 18 May 2009 19:43:56 +0000

 Module Name:	src
 Committed By:	bouyer
 Date:		Mon May 18 19:43:56 UTC 2009

 Modified Files:
 	src/sys/arch/x86/include [netbsd-5]: cacheinfo.h
 	src/usr.sbin/cpuctl/arch [netbsd-5]: i386.c

 Log Message:
 Pull up following revision(s) (requested by pgoyette in ticket #761):
 	sys/arch/x86/include/cacheinfo.h: revisions 1.11, 1.12
 	usr.sbin/cpuctl/arch/i386.c: revisions 1.18, 1.19 via patch
 1. Extend CPU probe of Intel processors to handle extended-models.  This
     allows us to properly identify new Intel 45nm processors, Core i7,
     Atom, and the 45nm Xeon MP.
 2. Properly decode several new Intel cache descriptors, as listed in the
     most recent (March 2009) edition of Intel's Application Note 485.
 Addresses my PR bin/41289
 Addresses my PR bin/41290


 To generate a diff of this commit:
 cvs rdiff -u -r1.9 -r1.9.8.1 src/sys/arch/x86/include/cacheinfo.h
 cvs rdiff -u -r1.13.2.2 -r1.13.2.3 src/usr.sbin/cpuctl/arch/i386.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

>Unformatted:

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