NetBSD Problem Report #42112
From track@Plectere.com Tue Sep 22 20:46:34 2009
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Message-Id: <200909222046.n8MKkRSm001687@Plectere.com>
Date: Tue, 22 Sep 2009 13:46:27 -0700 (PDT)
From: List Mail User <track@Plectere.com>
Reply-To: track@Plectere.com
To: gnats-bugs@gnats.NetBSD.org
Subject: 5.x/-current ACPI hangs machines which worked under 4.x
X-Send-Pr-Version: 3.95
>Number: 42112
>Category: kern
>Synopsis: 5.x/-current ACPI hangs machines which worked under 4.x
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: kern-bug-people
>State: open
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Tue Sep 22 20:50:00 +0000 2009
>Closed-Date:
>Last-Modified: Thu Apr 21 04:34:15 +0000 2011
>Originator: Paul Shupak
>Release: NetBSD 5.x+ (anything with the past 2 imports of ACPICA)
>Organization:
>Environment:
System: NetBSD -current
Architecture: i386 and amd64
Machine: i386 and amd64
>Description:
A particular model ECS motherboard, which worked previously with ACPI
now hangs during boot after printing the "attimer" or sometimes "pcppi" line.
>How-To-Repeat:
Boot any recent kernel (spring 2008+).
Below are appended a -current dmesg (ACPI disabled), an old dmesg
showing ACPI on 4.99.31 and the output of acpidump (for BIOS Rev 1.1B, which
is the latest, though the behavior is the same for 1.0A and 1.1A also).
BTW. "halt -p" or "shutdown -p" usually cause a panic on -current with
error messages regarding ACPI (Yes, even though ACPI is disabled).
--------------------------------------------------------------------------------
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 5.99.18 (GENERIC) #2: Sun Sep 20 09:46:18 PDT 2009
root@build:/space/obj-dirs/sys/arch/amd64/compile/GENERIC
total memory = 2047 MB
avail memory = 1970 MB
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
( )
mainbus0 (root)
mainbus0: Intel MP Specification (Version 1.4) (OEM00000 PROD00000000)
cpu0 at mainbus0 apid 0: AMD 686-class, 2199MHz, id 0xfc0
cpu0: AMD Cool`n'Quiet Technology 2200 MHz
cpu0: available frequencies (MHz): 1000 1800 2000 2200
cpu0: erratum 86 present
cpu0: erratum 89 present
cpu0: erratum 94 present
cpu0: erratum 97 present
cpu0: erratum 104 present
cpu0: erratum 101 present
cpu0: erratum 106 present
cpu0: erratum 107 present
cpu0: WARNING: errata present, BIOS upgrade may be
cpu0: WARNING: necessary to ensure reliable operation
mpbios: bus 0 is type PCI
mpbios: bus 1 is type PCI
mpbios: bus 2 is type ISA
ioapic0 at mainbus0 apid 2: pa 0xfec00000, version 14, 24 pins
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0: Silicon Integrated System 755 Host Bridge (rev. 0x01)
agp0 at pchb0: 1 Miscellaneous Control unit(s) found.
agp0: aperture at 0xd0000000, size 0x10000000
ppb0 at pci0 dev 1 function 0: Silicon Integrated System 86C202 (rev. 0x00)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
vga0 at pci1 dev 0 function 0: ATI Technologies Radeon 9600 AS (rev. 0x00)
wsdisplay0 at vga0 kbdmux 1: console (80x25, vt100 emulation)
wsmux1: connecting to wsdisplay0
radeondrm0 at vga0: ATI Radeon AS 9550
radeondrm0: AGP at 0xd0000000 256MB
radeondrm0: Initialized radeon 1.29.0 20080613
ATI Technologies product 0x4173 (miscellaneous display) at pci1 dev 0 function 1 not configured
pcib0 at pci0 dev 2 function 0: Silicon Integrated System 964 Host Bridge (rev. 0x36)
siside0 at pci0 dev 2 function 5
siside0: Silicon Integrated Systems 96X UDMA6755 IDE controller (rev. 0x01)
siside0: bus-master DMA support present
siside0: primary channel wired to compatibility mode
siside0: primary channel interrupting at ioapic0 pin 14
atabus0 at siside0 channel 0
siside0: secondary channel wired to compatibility mode
siside0: secondary channel interrupting at ioapic0 pin 15
atabus1 at siside0 channel 1
auich0 at pci0 dev 2 function 7: SiS 7012 AC-97 Audio
auich0: interrupting at ioapic0 pin 18
auich0: ac97: Avance Logic ALC655 codec; no 3D stereo
auich0: ac97: ext id 0x9c4<AC97_23,LDAC,SDAC,CDAC,SPDIF>
ohci0 at pci0 dev 3 function 0: Silicon Integrated System 5597/5598 USB Host Controller (rev. 0x0f)
ohci0: interrupting at ioapic0 pin 20
ohci0: OHCI version 1.0, legacy support
usb0 at ohci0: USB revision 1.0
ohci1 at pci0 dev 3 function 1: Silicon Integrated System 5597/5598 USB Host Controller (rev. 0x0f)
ohci1: interrupting at ioapic0 pin 21
ohci1: OHCI version 1.0, legacy support
usb1 at ohci1: USB revision 1.0
ohci2 at pci0 dev 3 function 2: Silicon Integrated System 5597/5598 USB Host Controller (rev. 0x0f)
ohci2: interrupting at ioapic0 pin 22
ohci2: OHCI version 1.0, legacy support
usb2 at ohci2: USB revision 1.0
ehci0 at pci0 dev 3 function 3: Silicon Integrated System 7002 USB 2.0 Host Controller (rev. 0x00)
ehci0: interrupting at ioapic0 pin 23
ehci0: EHCI version 1.0
ehci0: companion controllers, 3 ports each: ohci0 ohci1 ohci2
usb3 at ehci0: USB revision 2.0
sip0 at pci0 dev 4 function 0: SiS 900 10/100 Ethernet, rev 0x91
sip0: interrupting at ioapic0 pin 19
sip0: Ethernet address 00:11:5b:xx:xx:xx
rlphy0 at sip0 phy 1: RTL8201L 10/100 media interface, rev. 1
rlphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
re0 at pci0 dev 11 function 0: RealTek 8169/8110 Gigabit Ethernet (rev. 0x10)
re0: interrupting at ioapic0 pin 17
re0: Ethernet address xx:xx:xx:xx:xx:xx
re0: using 256 tx descriptors
rgephy0 at re0 phy 7: RTL8169S/8110S/8211 1000BASE-T media interface, rev. 0
rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
pchb1 at pci0 dev 24 function 0: Advanced Micro Devices K8 AMD64 HyperTransport Configuration (rev. 0x00)
pchb2 at pci0 dev 24 function 1: Advanced Micro Devices K8 AMD64 Address Map Configuration (rev. 0x00)
pchb3 at pci0 dev 24 function 2: Advanced Micro Devices K8 AMD64 DRAM Configuration (rev. 0x00)
pchb4 at pci0 dev 24 function 3: Advanced Micro Devices K8 AMD64 Miscellaneous Configuration (rev. 0x00)
isa0 at pcib0
lpt0 at isa0 port 0x378-0x37b irq 7
pckbc0 at isa0 port 0x60-0x64
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard, using wsdisplay0
pms0 at pckbc0 (aux slot)
pckbc0: using irq 12 for aux slot
wsmouse0 at pms0 mux 0
itesio0 at isa0 port 0x2e-0x2f: iTE IT8705F Super I/O (rev 2)
itesio0: Hardware Monitor registers at 0x290
fdc0 at isa0 port 0x3f0-0x3f7 irq 6 drq 2
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
audio0 at auich0: full duplex, independent
fd0 at fdc0 drive 0: 1.44MB, 80 cyl, 2 head, 18 sec
IPsec: Initialized Security Association Processing.
uhub0 at usb0: Silicon Integra OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 3 ports with 3 removable, self powered
uhub1 at usb1: Silicon Integra OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1: 3 ports with 3 removable, self powered
uhub2 at usb2: Silicon Integra OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub2: 2 ports with 2 removable, self powered
uhub3 at usb3: Silicon Integrated System EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub3: 8 ports with 8 removable, self powered
wd0 at atabus0 drive 0: <ST3160023A>
wd0: quirks 0x2<FORCE_LBA48>
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 149 GB, 310101 cyl, 16 head, 63 sec, 512 bytes/sect x 312581808 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
wd0(siside0:0:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using DMA)
wd1 at atabus1 drive 0: <ST3160023A>
wd1: quirks 0x2<FORCE_LBA48>
wd1: drive supports 16-sector PIO transfers, LBA48 addressing
wd1: 149 GB, 310101 cyl, 16 head, 63 sec, 512 bytes/sect x 312581808 sectors
wd1: 32-bit data port
wd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
wd1(siside0:1:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using DMA)
Kernelized RAIDframe activated
pad0: outputs: 44100Hz, 16-bit, stereo
audio1 at pad0: half duplex
Component on: wd0e: 297516240
Row: 0 Column: 0 Num Rows: 1 Num Columns: 2
Version: 2 Serial Number: 75319842 Mod Counter: 799
Clean: No Status: 0
sectPerSU: 128 SUsPerPU: 1 SUsPerRU: 1
RAID Level: 1 blocksize: 512 numBlocks: 297516160
Autoconfig: Yes
Contains root partition: Yes
Last configured as: raid0
Component on: wd1e: 297516240
Row: 0 Column: 1 Num Rows: 1 Num Columns: 2
Version: 2 Serial Number: 75319842 Mod Counter: 799
Clean: No Status: 0
sectPerSU: 128 SUsPerPU: 1 SUsPerRU: 1
RAID Level: 1 blocksize: 512 numBlocks: 297516160
Autoconfig: Yes
Contains root partition: Yes
Last configured as: raid0
Found: wd0e at 0
Found: wd1e at 1
RAID autoconfigure
Configuring raid0:
Starting autoconfiguration of RAID set...
Looking for 0 in autoconfig
Found: wd0e at 0
Looking for 1 in autoconfig
Found: wd1e at 1
raid0: allocating 20 buffers of 65536 bytes.
raid0: RAID Level 1
raid0: Components: /dev/wd0e /dev/wd1e
raid0: Total Sectors: 297516160 (145271 MB)
boot device: raid0
root on raid0a dumps on raid0b
mountroot: trying smbfs...
mountroot: trying ntfs...
mountroot: trying nfs...
mountroot: trying msdos...
mountroot: trying lfs...
mountroot: trying ext2fs...
mountroot: trying ffs...
root file system type: ffs
init: copying out path `/sbin/init' 11
raid0: Device already configured!
wsdisplay0: screen 1 added (80x25, vt100 emulation)
wsdisplay0: screen 2 added (80x25, vt100 emulation)
wsdisplay0: screen 3 added (80x25, vt100 emulation)
wsdisplay0: screen 4 added (80x25, vt100 emulation)
--------------------------------------------------------------------------------
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 4.99.31 (ATHALON64-2800) #49: Tue Oct 2 14:45:55 PDT 2007
root@build:/usr/src/sys/arch/amd64/compile/ATHALON64-2800
total memory = 1023 MB
avail memory = 974 MB
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
mainbus0 (root)
cpu0 at mainbus0 apid 0: (boot processor)
cpu0: AMD Athlon(tm) 64 Processor 2800+, 1799.54 MHz
cpu0: features: e7dbfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features: e7dbfbff<PGE,MCA,CMOV,PAT,PSE36,MPC,NOX,MMXX,MMX>
cpu0: features: e7dbfbff<FXSR,SSE,SSE2,LONG,3DNOW2,3DNOW>
cpu0: I-cache 64 KB 64B/line 2-way, D-cache 64 KB 64B/line 2-way
cpu0: L2 cache 512 KB 64B/line 16-way
cpu0: ITLB 32 4 KB entries fully associative, 8 4 MB entries fully associative
cpu0: DTLB 32 4 KB entries fully associative, 8 4 MB entries fully associative
cpu0: AMD Power Management features: f<TTP,VID,FID,TS>
cpu0: WARNING: AMD errata present, BIOS upgrade may be
cpu0: WARNING: necessary to ensure reliable operation
cpu0: calibrating local timer
cpu0: apic clock running at 199 MHz
cpu0: 8 page colors
ioapic0 at mainbus0 apid 2
ioapic0: pa 0xfec00000, version 14, 24 pins
acpi0 at mainbus0: Advanced Configuration and Power Interface
acpi0: using Intel ACPI CA subsystem version 20060217
acpi0: X/RSDT: OemId <AWARD ,AWRDACPI,42302e31>, AslId <AWRD,00000000>
acpi0: SCI interrupting at int 9
acpi0: fixed-feature power button present
timecounter: Timecounter "ACPI-Fast" frequency 3579545 Hz quality 1000
ACPI-Fast 24-bit timer
mpacpi: could not get bus number, assuming bus 0
CPU0 (ACPI Object Type 'Processor' [0x0c]) at acpi0 not configured
acpibut0 at acpi0 (PWRB, PNP0C0C): ACPI Power Button
acpibut1 at acpi0 (FUTS, PNP0C0E): ACPI Sleep Button
MEM (PNP0C01) [System Board] at acpi0 not configured
PCI0 (PNP0A03) [PCI/PCI-X Host Bridge] at acpi0 not configured
LNKA (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
LNKB (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
LNKC (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
LNKD (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
LNKE (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
LNKF (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
LNKG (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
LNKH (PNP0C0F) [PCI interrupt link device] at acpi0 not configured
SYSR (PNP0C02) [Plug and Play motherboard register resources] at acpi0 not configured
PIC (PNP0000) [AT Interrupt Controller] at acpi0 not configured
DMA1 (PNP0200) [AT DMA Controller] at acpi0 not configured
attimer0 at acpi0 (TMR, PNP0100): AT Timer
attimer0: io 0x40-0x43 irq 0
RTC (PNP0B00) [AT Real-Time Clock] at acpi0 not configured
pcppi1 at acpi0 (SPKR, PNP0800)
pcppi1: io 0x61
midi0 at pcppi1: PC speaker (CPU-intensive output)
spkr0 at pcppi1
sysbeep0 at pcppi1
COPR (PNP0C04) [Math Coprocessor] at acpi0 not configured
fdc0 at acpi0 (FDC0, PNP0700)
fdc0: io 0x3f0-0x3f5,0x3f7 irq 6 drq 2
com0 at acpi0 (UAR1, PNP0501-1)
com0: io 0x3f8-0x3ff irq 4
com0: ns16550a, working fifo
lpt0 at acpi0 (ECP1, PNP0401-1)
lpt0: io 0x378-0x37f,0x778-0x77b irq 7 drq 3
pckbc0 at acpi0 (PS2K, PNP0303): kbd port
pckbc0: io 0x60,0x64 irq 1
FAN (PNP0C0B) [ACPI Fan] at acpi0 not configured
acpitz0 at acpi0 (THRM): ACPI Thermal Zone
acpitz0: unable to get polling interval; using default of 30.0s
acpitz0: active cooling level 0: 63.0C
acpitz0: critical 65.0C passive 45.0C
pcppi1: attached to attimer0
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0: PCI configuration registers:
Common header:
0x00: 0x07551039 0x22100007 0x06000001 0x00002000
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 755 Host Bridge (0x0755)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x2210
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: on
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x01
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0xe0000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x000000a0 0x00000000 0x000000ff
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xe0000000, not sized
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0xa0
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0xff
Capability register at 0xa0
type: 0x02 (AGP, rev. 3.0)
Capability register at 0xd0
type: 0x08 (LDT)
Capability register at 0xf0
type: 0x08 (LDT)
Device-dependent header:
0x40: 0x17740016 0xa090ff0c 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x0030803c 0x00000000 0x00000000 0x10210000
0x80: 0x00000000 0xc8140000 0x10000000 0x02000300
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x0030d002 0x1f004e1b 0x00000200 0x00000000
0xb0: 0x00000000 0x00010f20 0x00000000 0x00000000
0xc0: 0x00180800 0x28458802 0x00000000 0x00000100
0xd0: 0x0120f008 0x11110060 0x777700d0 0x00350522
0xe0: 0x00000002 0x00000000 0x00000000 0x00000000
0xf0: 0x80000008 0x00178014 0x00000000 0x00557979
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 755 Host Bridge (host bridge, revision 0x01) at ? dev 0 function 0 (intrswiz 0, intrpin 0, i/o on, mem on, no quirks)
pchb0: Silicon Integrated System 755 Host Bridge (rev. 0x01)
agp0 at pchb0: aperture at 0xe0000000, size 0x400000
ppb0 at pci0 dev 1 function 0: PCI configuration registers:
Common header:
0x00: 0x00021039 0x02200107 0x06040000 0x00016300
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 86C202 (0x0002)
Command register: 0x0107
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): on
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0220
Capability List support: off
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: PCI (0x04)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x01 (0x01)
Latency Timer: 0x63
Cache Line Size: 0x00
Type 1 (PCI-PCI bridge) header:
0x10: 0x00000000 0x00000000 0x20010100 0x2220d0d0
0x20: 0xe800e800 0xdff0c000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x000e0000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Primary bus number: 0x00
Secondary bus number: 0x01
Subordinate bus number: 0x01
Secondary bus latency timer: 0x20
Secondary status register: 0x2220
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Signaled Target Abort: off
Received Target Abort: off
Received Master Abort: on
System Error: off
Parity Error: off
I/O region:
base register: 0xd0
limit register: 0xd0
base upper 16 bits register: 0x0000
limit upper 16 bits register: 0x0000
Memory region:
base register: 0xe800
limit register: 0xe800
Prefetchable memory region:
base register: 0xc000
limit register: 0xdff0
base upper 32 bits register: 0x00000000
limit upper 32 bits register: 0x00000000
Reserved @ 0x34: 0x00000000
Expansion ROM Base Address: 0x00000000
Interrupt line: 0x00
Interrupt pin: 0x00 (none)
Bridge control register: 0x000e
Parity error response: off
Secondary SERR forwarding: on
ISA enable: on
VGA enable: on
Master abort reporting: off
Secondary bus reset: off
Fast back-to-back capable: off
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x00004002 0x00800009 0x00000008 0x00000000
0x60: 0x60600630 0x000012aa 0x15982323 0x000a0707
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x18151815
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 86C202 (PCI bridge) at ? dev 1 function 0 (intrswiz 0, intrpin 0, i/o on, mem on, no quirks): Silicon Integrated System 86C202 (rev. 0x00)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
vga0 at pci1 dev 0 function 0: PCI configuration registers:
Common header:
0x00: 0x41531002 0x02b00007 0x03000000 0x00802008
Vendor Name: ATI Technologies (0x1002)
Device Name: Radeon 9600 AS (0x4153)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x02b0
Capability List support: on
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: display (0x03)
Subclass Name: VGA (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0xc0000008 0x0000d001 0xe8020000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x04021002
0x30: 0x00000000 0x00000058 0x00000000 0x00080103
Base address register at 0x10
type: 32-bit prefetchable memory
base: 0xc0000000, size: 0x10000000
Base address register at 0x14
type: 32-bit i/o
base: 0x0000d000, size: 0x00000100
Base address register at 0x18
type: 32-bit nonprefetchable memory
base: 0xe8020000, size: 0x00010000
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1002
Subsystem ID: 0x0402
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x58
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x08
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x03
Capability register at 0x58
type: 0x02 (AGP, rev. 3.0)
Capability register at 0x50
type: 0x01 (Power Management, rev. 1.0)
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x04021002
0x50: 0x06020001 0x00000000 0x00305002 0xff00021b
0x60: 0x00000200 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000005 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
ATI Technologies Radeon 9600 AS (VGA display) at ? dev 0 function 0 (intrswiz 0, intrpin 0x1, i/o on, mem on, no quirks): ATI Technologies Radeon 9600 AS (rev. 0x00)
wsdisplay0 at vga0 kbdmux 1: console (80x25, vt100 emulation), using wskbd0
wsmux1: connecting to wsdisplay0
direct rendering for vga0 unsupported
ATI Technologies product 0x4173 (miscellaneous display) at pci1 dev 0 function 1: PCI configuration registers:
Common header:
0x00: 0x41731002 0x02b00000 0x03800000 0x00002008
Vendor Name: ATI Technologies (0x1002)
Device ID: 0x4173
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x02b0
Capability List support: on
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: display (0x03)
Subclass Name: miscellaneous (0x80)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0xd0000008 0xe8030000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x04031002
0x30: 0x00000000 0x00000050 0x00000000 0x000800ff
Base address register at 0x10
type: 32-bit prefetchable memory
base: 0xd0000000, size: 0x10000000
Base address register at 0x14
type: 32-bit nonprefetchable memory
base: 0xe8030000, size: 0x00010000
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1002
Subsystem ID: 0x0403
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x08
Interrupt pin: 0x00 (none)
Interrupt line: 0xff
Capability register at 0x50
type: 0x01 (Power Management, rev. 1.0)
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x06020001 0x00000000 0x00305002 0xff00021b
0x60: 0x00000200 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
ATI Technologies product 0x4173 (miscellaneous display) at pci1 dev 0 function 1 (intrswiz 0, intrpin 0, i/o off, mem off, no quirks) not configured
pcib0 at pci0 dev 2 function 0: PCI configuration registers:
Common header:
0x00: 0x09641039 0x0200000f 0x06010036 0x00800000
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 964 Host Bridge (0x0964)
Command register: 0x000f
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: on
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0200
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: ISA (0x01)
Interface: 0x00
Revision ID: 0x36
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x0a0b0392 0xdd3d6005 0x00000010 0x01042011
0x50: 0x01022811 0x0a200a60 0x00120000 0x00000500
0x60: 0x090b0a05 0x128ec1ff 0x46008009 0x14020097
0x70: 0xffff0000 0x3e031000 0x80200020 0x40000002
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x0000001f 0x00000001 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00100001 0x00000000 0x0030803c 0x41000000
0xd0: 0x01000c20 0x00326222 0x2a040085 0xaaaaaaaa
0xe0: 0xf8000040 0x00442042 0x00000000 0x00000000
0xf0: 0x0000000a 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 964 Host Bridge (ISA bridge, revision 0x36) at ? dev 2 function 0 (intrswiz 0, intrpin 0, i/o on, mem on, no quirks)
pcib0: Silicon Integrated System 964 Host Bridge (rev. 0x36)
siside0 at pci0 dev 2 function 5: PCI configuration registers:
Common header:
0x00: 0x55131039 0x02000005 0x01018001 0x00008000
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 5597/5598 IDE controller (0x5513)
Command register: 0x0005
I/O space accesses: on
Memory space accesses: off
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0200
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: mass storage (0x01)
Subclass Name: IDE (0x01)
Interface: 0x80
Revision ID: 0x01
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x80
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000001 0x00000001 0x00000001 0x00000001
0x20: 0x00004001 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
type: 16-bit i/o
base: 0x00000000, size: 0x00000000
Base address register at 0x14
type: 16-bit i/o
base: 0x00000000, size: 0x00000000
Base address register at 0x18
type: 16-bit i/o
base: 0x00000000, size: 0x00000000
Base address register at 0x1c
type: 16-bit i/o
base: 0x00000000, size: 0x00000000
Base address register at 0x20
type: 16-bit i/o
base: 0x00004000, size: 0x00000010
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00060000 0x00000000
0x50: 0x21922192 0xc0d5962a 0x00000000 0x00000000
0x60: 0xaafbaafb 0x00000000 0x00c80080 0x00000000
0x70: 0x04062116 0x1e1c6000 0x04062126 0x1e1c6000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 5597/5598 IDE controller (IDE mass storage, interface 0x80, revision 0x01) at ? dev 2 function 5 (intrswiz 0, intrpin 0, i/o on, mem off, no quirks)
siside0: Silicon Integrated Systems 96X UDMA6755 IDE controller (rev. 0x01)
siside0: bus-master DMA support present
siside0: primary channel wired to compatibility mode
siside0: primary channel interrupting at ioapic0 pin 14 (irq 14)
atabus0 at siside0 channel 0
siside0: secondary channel wired to compatibility mode
siside0: secondary channel interrupting at ioapic0 pin 15 (irq 15)
atabus1 at siside0 channel 1
auich0 at pci0 dev 2 function 7: PCI configuration registers:
Common header:
0x00: 0x70121039 0x02900005 0x040100a0 0x00002000
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 7012 AC-97 Sound (0x7012)
Command register: 0x0005
I/O space accesses: on
Memory space accesses: off
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0290
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: multimedia (0x04)
Subclass Name: audio (0x01)
Interface: 0x00
Revision ID: 0xa0
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x0000e001 0x0000e101 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x00000048 0x00000000 0x0b34030a
Base address register at 0x10
type: 32-bit i/o
base: 0x0000e000, size: 0x00000100
Base address register at 0x14
type: 32-bit i/o
base: 0x0000e100, size: 0x00000080
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x48
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x0b
Minimum Grant: 0x34
Interrupt pin: 0x03 (pin C)
Interrupt line: 0x0a
Capability register at 0x48
type: 0x01 (Power Management, rev. 1.0)
Device-dependent header:
0x40: 0x00000004 0x00000000 0xc6420001 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000003 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 7012 AC-97 Sound (audio multimedia, revision 0xa0) at ? dev 2 function 7 (intrswiz 0, intrpin 0x3, i/o on, mem off, no quirks): SiS 7012 AC-97 Audio
auich0: interrupting at ioapic0 pin 18 (irq 10)
auich0: ac97: Avance Logic ALC655 codec; no 3D stereo
auich0: ac97: ext id 9c4<AC97_23,LDAC,SDAC,CDAC,SPDIF>
ohci0 at pci0 dev 3 function 0: PCI configuration registers:
Common header:
0x00: 0x70011039 0x82800007 0x0c03100f 0x00802008
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 5597/5598 USB host controller (0x7001)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x8280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: on
Class Name: serial bus (0x0c)
Subclass Name: USB (0x03)
Interface: 0x10
Revision ID: 0x0f
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0xe8124000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x00000000 0x00000000 0x50000105
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xe8124000, size: 0x00001000
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x50
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x05
Device-dependent header:
0x40: 0x00000000 0x0001ae5c 0x0000023f 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0xc9c20001
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 5597/5598 USB host controller (USB serial bus, interface 0x10, revision 0x0f) at ? dev 3 function 0 (intrswiz 0, intrpin 0x1, i/o on, mem on, no quirks): Silicon Integrated System 5597/5598 USB host controller (rev. 0x0f)
ohci0: interrupting at ioapic0 pin 20 (irq 5)
ohci0: OHCI version 1.0, legacy support
usb0 at ohci0: USB revision 1.0
uhub0 at usb0
uhub0: Silicon Integra OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 3 ports with 3 removable, self powered
ohci1 at pci0 dev 3 function 1: PCI configuration registers:
Common header:
0x00: 0x70011039 0x82800007 0x0c03100f 0x00002008
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 5597/5598 USB host controller (0x7001)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x8280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: on
Class Name: serial bus (0x0c)
Subclass Name: USB (0x03)
Interface: 0x10
Revision ID: 0x0f
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0xe8120000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x00000000 0x00000000 0x5000020a
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xe8120000, size: 0x00001000
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x50
Minimum Grant: 0x00
Interrupt pin: 0x02 (pin B)
Interrupt line: 0x0a
Device-dependent header:
0x40: 0x00000000 0x0001ae5c 0x0000023f 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0xc9c20001
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 5597/5598 USB host controller (USB serial bus, interface 0x10, revision 0x0f) at ? dev 3 function 1 (intrswiz 0, intrpin 0x2, i/o on, mem on, no quirks): Silicon Integrated System 5597/5598 USB host controller (rev. 0x0f)
ohci1: interrupting at ioapic0 pin 21 (irq 10)
ohci1: OHCI version 1.0, legacy support
usb1 at ohci1: USB revision 1.0
uhub1 at usb1
uhub1: Silicon Integra OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1: 3 ports with 3 removable, self powered
ohci2 at pci0 dev 3 function 2: PCI configuration registers:
Common header:
0x00: 0x70011039 0x82800007 0x0c03100f 0x00002008
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 5597/5598 USB host controller (0x7001)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x8280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: on
Class Name: serial bus (0x0c)
Subclass Name: USB (0x03)
Interface: 0x10
Revision ID: 0x0f
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0xe8121000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x00000000 0x00000000 0x5000030b
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xe8121000, size: 0x00001000
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x50
Minimum Grant: 0x00
Interrupt pin: 0x03 (pin C)
Interrupt line: 0x0b
Device-dependent header:
0x40: 0x00000000 0x0001ae5c 0x0000027f 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0xc9c20001
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 5597/5598 USB host controller (USB serial bus, interface 0x10, revision 0x0f) at ? dev 3 function 2 (intrswiz 0, intrpin 0x3, i/o on, mem on, no quirks): Silicon Integrated System 5597/5598 USB host controller (rev. 0x0f)
ohci2: interrupting at ioapic0 pin 22 (irq 11)
ohci2: OHCI version 1.0, legacy support
usb2 at ohci2: USB revision 1.0
uhub2 at usb2
uhub2: Silicon Integra OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub2: 2 ports with 2 removable, self powered
ehci0 at pci0 dev 3 function 3: PCI configuration registers:
Common header:
0x00: 0x70021039 0x02900006 0x0c032000 0x00002008
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 7002 USB 2.0 host controller (0x7002)
Command register: 0x0006
I/O space accesses: off
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0290
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: serial bus (0x0c)
Subclass Name: USB (0x03)
Interface: 0x20
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0xe8122000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x00000050 0x00000000 0x50000409
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0xe8122000, size: 0x00001000
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x50
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x50
Minimum Grant: 0x00
Interrupt pin: 0x04 (pin D)
Interrupt line: 0x09
Capability register at 0x50
type: 0x01 (Power Management, rev. 1.0)
Device-dependent header:
0x40: 0x08000080 0x00000000 0x00000000 0x00000000
0x50: 0xc9c20001 0x00000000 0x2100000a 0x00000000
0x60: 0x01ff2020 0x00000000 0x00000000 0x00000000
0x70: 0x01000001 0xe0000000 0x3fdf0000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 7002 USB 2.0 host controller (USB serial bus, interface 0x20) at ? dev 3 function 3 (intrswiz 0, intrpin 0x4, i/o off, mem on, no quirks): Silicon Integrated System 7002 USB 2.0 host controller (rev. 0x00)
ehci0: interrupting at ioapic0 pin 23 (irq 9)
ehci0: BIOS has given up ownership
ehci0: EHCI version 1.0
ehci0: companion controllers, 3 ports each: ohci0 ohci1 ohci2
usb3 at ehci0: USB revision 2.0
uhub3 at usb3
uhub3: Silicon Integrated System EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub3: 8 ports with 8 removable, self powered
sip0 at pci0 dev 4 function 0: PCI configuration registers:
Common header:
0x00: 0x09001039 0x02900007 0x02000091 0x00002000
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 900 10/100 Ethernet (0x0900)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0290
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: network (0x02)
Subclass Name: ethernet (0x00)
Interface: 0x00
Revision ID: 0x91
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x0000e201 0xe8123000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x18911019
0x30: 0x00000000 0x00000040 0x00000000 0x0b340105
Base address register at 0x10
type: 32-bit i/o
base: 0x0000e200, size: 0x00000100
Base address register at 0x14
type: 32-bit nonprefetchable memory
base: 0xe8123000, size: 0x00001000
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x40
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x0b
Minimum Grant: 0x34
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x05
Capability register at 0x40
type: 0x01 (Power Management, rev. 1.0)
Device-dependent header:
0x40: 0xfe020001 0x00000000 0x00000000 0x00000000
0x50: 0x00000001 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000091 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 900 10/100 Ethernet (ethernet network, revision 0x91) at ? dev 4 function 0 (intrswiz 0, intrpin 0x1, i/o on, mem on, no quirks): SiS 900 10/100 Ethernet, rev 0x91
sip0: interrupting at ioapic0 pin 19 (irq 5)
sip0: Ethernet address 00:11:5b:xx:xx:xx
rlphy0 at sip0 phy 1: RTL8201L 10/100 media interface, rev. 1
rlphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
siside1 at pci0 dev 5 function 0: PCI configuration registers:
Common header:
0x00: 0x01801039 0x02300005 0x01018501 0x00002000
Vendor Name: Silicon Integrated System (0x1039)
Device Name: 180 SATA controller (0x0180)
Command register: 0x0005
I/O space accesses: on
Memory space accesses: off
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0230
Capability List support: on
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: mass storage (0x01)
Subclass Name: IDE (0x01)
Interface: 0x85
Revision ID: 0x01
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x0000e301 0x0000e401 0x0000e501 0x0000e601
0x20: 0x0000e701 0x0000e801 0x00000000 0x18911019
0x30: 0x00000000 0x00000058 0x00000000 0x0000010b
Base address register at 0x10
type: 16-bit i/o
base: 0x0000e300, size: 0x00000008
Base address register at 0x14
type: 16-bit i/o
base: 0x0000e400, size: 0x00000004
Base address register at 0x18
type: 16-bit i/o
base: 0x0000e500, size: 0x00000008
Base address register at 0x1c
type: 16-bit i/o
base: 0x0000e600, size: 0x00000004
Base address register at 0x20
type: 16-bit i/o
base: 0x0000e700, size: 0x00000010
Base address register at 0x24
type: 16-bit i/o
base: 0x0000e800, size: 0x00000080
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1019
Subsystem ID: 0x1891
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x58
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0b
Capability register at 0x58
type: 0x01 (Power Management, rev. 1.0)
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x00920092 0x14c40000 0x80020001 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x407233ba 0x407233ba 0x00000000 0x00000000
0x90: 0x00000008 0x00000000 0x100c04cc 0x05c005c0
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00180001 0x00000000 0x00000000
0xd0: 0x00000000 0x00180001 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Silicon Integrated System 180 SATA controller (IDE mass storage, interface 0x85, revision 0x01) at ? dev 5 function 0 (intrswiz 0, intrpin 0x1, i/o on, mem off, no quirks)
siside1: Silicon Integrated Systems 180/96X SATA controller (rev. 0x01)
siside1: bus-master DMA support present
siside1: primary channel wired to native-PCI mode
siside1: using ioapic0 pin 17 (irq 11) for native-PCI interrupt
atabus2 at siside1 channel 0
siside1: secondary channel wired to native-PCI mode
atabus3 at siside1 channel 1
re0 at pci0 dev 10 function 0: PCI configuration registers:
Common header:
0x00: 0x816910ec 0x02b00007 0x02000010 0x00002008
Vendor Name: Realtek Semiconductor (0x10ec)
Device Name: 8169/S/SB 10/100/1000 Ethernet (0x8169)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x02b0
Capability List support: on
66 MHz capable: on
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: network (0x02)
Subclass Name: ethernet (0x00)
Interface: 0x00
Revision ID: 0x10
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0x0000e901 0xe8125000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x816910ec
0x30: 0x00000000 0x000000dc 0x00000000 0x4020010a
Base address register at 0x10
type: 32-bit i/o
base: 0x0000e900, size: 0x00000100
Base address register at 0x14
type: 32-bit nonprefetchable memory
base: 0xe8125000, size: 0x00000100
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x10ec
Subsystem ID: 0x8169
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0xdc
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x40
Minimum Grant: 0x20
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0a
Capability register at 0xdc
type: 0x01 (Power Management, rev. 1.0)
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0xf7c20001
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Realtek Semiconductor 8169/S/SB 10/100/1000 Ethernet (ethernet network, revision 0x10) at ? dev 10 function 0 (intrswiz 0, intrpin 0x1, i/o on, mem on, no quirks): RealTek 8169/8110 Gigabit Ethernet (rev. 0x10)
re0: interrupting at ioapic0 pin 18 (irq 10)
re0: Ethernet address 00:40:xx:xx:xx:xx
re0: using 256 tx descriptors
rgephy0 at re0 phy 7: RTL8169S/8110S 1000BASE-T media interface, rev. 0
rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FDX, auto
pchb1 at pci0 dev 24 function 0: PCI configuration registers:
Common header:
0x00: 0x11001022 0x00100000 0x06000000 0x00800000
Vendor Name: Advanced Micro Devices (0x1022)
Device Name: K8 AMD64 HyperTransport configuration (0x1100)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0010
Capability List support: on
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000080 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Capability list pointer: 0x80
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Capability register at 0x80
type: 0x08 (LDT)
Device-dependent header:
0x40: 0x00010101 0x00010101 0x00010101 0x00010101
0x50: 0x00010101 0x00010101 0x00010101 0x00010101
0x60: 0x00000000 0x000000e4 0x0f00cc0f 0x0000000c
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x21010008 0x11110020 0x80750522 0x00000002
0x90: 0x02510456 0x00ff0000 0x00000007 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Advanced Micro Devices K8 AMD64 HyperTransport configuration (host bridge) at ? dev 24 function 0 (intrswiz 0, intrpin 0, i/o off, mem off, no quirks)
pchb1: Advanced Micro Devices K8 AMD64 HyperTransport configuration (rev. 0x00)
pchb2 at pci0 dev 24 function 1: PCI configuration registers:
Common header:
0x00: 0x11011022 0x00000000 0x06000000 0x00800000
Vendor Name: Advanced Micro Devices (0x1022)
Device Name: K8 AMD64 Address Map configuration (0x1101)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0000
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000003 0x003f0000 0x00400000 0x00000001
0x50: 0x00400000 0x00000002 0x00400000 0x00000003
0x60: 0x00400000 0x00000004 0x00400000 0x00000005
0x70: 0x00400000 0x00000006 0x00400000 0x00000007
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00002000 0x00000000 0x00000000
0xb0: 0x00000a03 0x00000b00 0x00400003 0x00ffff00
0xc0: 0x00000000 0x00000000 0x00001013 0x000ff000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0xff000003 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Advanced Micro Devices K8 AMD64 Address Map configuration (host bridge) at ? dev 24 function 1 (intrswiz 0, intrpin 0, i/o off, mem off, no quirks)
pchb2: Advanced Micro Devices K8 AMD64 Address Map configuration (rev. 0x00)
pchb3 at pci0 dev 24 function 2: PCI configuration registers:
Common header:
0x00: 0x11021022 0x00000000 0x06000000 0x00800000
Vendor Name: Advanced Micro Devices (0x1022)
Device Name: K8 AMD64 DRAM configuration (0x1102)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0000
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000001 0x00000801 0x00001001 0x00001801
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x03e0e600 0x03e0e600 0x03e0e600 0x03e0e600
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000033 0x00000000 0x13823552 0x00000b31
0x90: 0x080c8c00 0x3e7b0606 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x384b78f4 0x00000012 0x2d16efcf 0xff04ffb4
0xc0: 0x00010000 0x00002000 0x00000000 0x00000000
0xd0: 0xc66bc2ce 0x0b0cdff0 0x7a35e2d9 0x3f34f4db
0xe0: 0xe77be84b 0x2656d0f8 0x1a01f30b 0x5f98f0db
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Advanced Micro Devices K8 AMD64 DRAM configuration (host bridge) at ? dev 24 function 2 (intrswiz 0, intrpin 0, i/o off, mem off, no quirks)
pchb3: Advanced Micro Devices K8 AMD64 DRAM configuration (rev. 0x00)
pchb4 at pci0 dev 24 function 3: PCI configuration registers:
Common header:
0x00: 0x11031022 0x00000000 0x06000000 0x00800000
Vendor Name: Advanced Micro Devices (0x1022)
Device Name: K8 AMD64 Miscellaneous configuration (0x1103)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Interrupt disable: off
Status register: 0x0000
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: fast (0x0)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000000 0x00000040 0x00010c0f 0xa2000040
0x50: 0x00000000 0x00000000 0x00000000 0x7dc63740
0x60: 0x0000006d 0x00000000 0x00000000 0x00000000
0x70: 0x51020111 0x50008011 0x08003800 0x0000221b
0x80: 0x23070000 0x21132113 0x00000000 0x00000000
0x90: 0x00000004 0x00000070 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x6000003b 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x000d0701 0x00000000 0x00000000
0xe0: 0x00000000 0x00630c20 0x00000108 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Advanced Micro Devices K8 AMD64 Miscellaneous configuration (host bridge) at ? dev 24 function 3 (intrswiz 0, intrpin 0, i/o off, mem off, no quirks)
pchb4: Advanced Micro Devices K8 AMD64 Miscellaneous configuration (rev. 0x00)
isa0 at pcib0
it0 at isa0 port 0x290-0x297: IT8705F Hardware monitor
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
fd0 at fdc0 drive 0: 1.44MB, 80 cyl, 2 head, 18 sec
wd0 at atabus0 drive 0: <WDC WD400EB-00CPF0>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 38166 MB, 77545 cyl, 16 head, 63 sec, 512 bytes/sect x 78165360 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
wd0(siside0:0:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using DMA)
atapibus0 at atabus1: 2 targets
cd0 at atapibus0 drive 0: <CD-RW IDE5232, , VER 000> cdrom removable
cd0: 32-bit data port
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 4 (Ultra/66)
cd0(siside0:1:0): using PIO mode 4, Ultra-DMA mode 4 (Ultra/66) (using DMA)
audio0 at auich0: full duplex, independent
Kernelized RAIDframe activated
IPsec: Initialized Security Association Processing.
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
wsdisplay0: screen 1 added (80x25, vt100 emulation)
wsdisplay0: screen 2 added (80x25, vt100 emulation)
wsdisplay0: screen 3 added (80x25, vt100 emulation)
wsdisplay0: screen 4 added (80x25, vt100 emulation)
--------------------------------------------------------------------------------
/*
RSD PTR: Checksum=164, OEMID=AWARD, RsdtAddress=0x7fff3000
*/
/*
RSDT: Length=44, Revision=1, Checksum=102,
OEMID=AWARD, OEM Table ID=AWRDACPI, OEM Revision=0x42302e31,
Creator ID=AWRD, Creator Revision=0x0
*/
/*
Entries={ 0x7fff3040, 0x7fff6b80 }
*/
/*
DSDT=0x7fff30c0
INT_MODEL=APIC
SCI_INT=9
SMI_CMD=0x1048, ACPI_ENABLE=0x81, ACPI_DISABLE=0x80, S4BIOS_REQ=0x0
PM1a_EVT_BLK=0x1000-0x1003
PM1a_CNT_BLK=0x1004-0x1005
PM2_CNT_BLK=0x1016-0x1016
PM2_TMR_BLK=0x1008-0x100b
PM2_GPE0_BLK=0x1020-0x1023
PM2_GPE1_BLK=0x1030-0x1033, GPE1_BASE=16
P_LVL2_LAT=90ms, P_LVL3_LAT=900ms
FLUSH_SIZE=0, FLUSH_STRIDE=0
DUTY_OFFSET=1, DUTY_WIDTH=0
DAY_ALRM=126, MON_ALRM=127, CENTURY=0
Flags={WBINVD,PROC_C1,SLP_BUTTON,RTC_S4}
*/
/*
DSDT: Length=15035, Revision=1, Checksum=35,
OEMID=AWARD, OEM Table ID=AWRDACPI, OEM Revision=0x1000,
Creator ID=MSFT, Creator Revision=0x100000e
*/
DefinitionBlock ("acpi_dst.aml", "DSDT", 0x1, "AWARD", "AWRDACPI", 0x1000)
{
Scope(\_PR) {
Processor(\_PR.CPU0, 0, 0x0, 0x0) {
}
}
Name(\_S0, Package(0x04) {
0x00,
0x00,
0x00,
0x00,
})
Name(\_S1, Package(0x04) {
0x01,
0x01,
0x01,
0x01,
})
Name(\SS3, Package(0x04) {
0x03,
0x03,
0x03,
0x03,
})
Name(\_S4, Package(0x04) {
0x04,
0x04,
0x04,
0x04,
})
Name(\_S5, Package(0x04) {
0x05,
0x05,
0x05,
0x05,
})
OperationRegion(\DEBG, SystemIO, 0x80, 0x01)
Field(\DEBG, ByteAcc, NoLock, Preserve) {
DBG1, 8
}
OperationRegion(\P06, SystemIO, 0x1006, 0x01)
Field(\P06, ByteAcc, NoLock, Preserve) {
P6, 8
}
OperationRegion(\P01, SystemIO, 0x1001, 0x01)
Field(\P01, ByteAcc, NoLock, Preserve) {
P1, 8
}
OperationRegion(PR48, SystemIO, 0x1048, 0x01)
Field(PR48, ByteAcc, NoLock, Preserve) {
P48, 8
}
OperationRegion(\PR49, SystemIO, 0x1049, 0x01)
Field(\PR49, ByteAcc, NoLock, Preserve) {
P49, 8
}
OperationRegion(\TRAP, SystemIO, 0x1050, 0x02)
Field(\TRAP, WordAcc, NoLock, Preserve) {
TRA0, 16
}
OperationRegion(EXTM, SystemMemory, 0x000ff830, 0x10)
Field(EXTM, WordAcc, NoLock, Preserve) {
ROM1, 16,
RMS1, 16,
ROM2, 16,
RMS2, 16,
ROM3, 16,
RMS3, 16,
AMEM, 32
}
OperationRegion(\PR20, SystemIO, 0x1020, 0x02)
Field(\PR20, WordAcc, NoLock, Preserve) {
P20, 16
}
OperationRegion(\PR22, SystemIO, 0x1022, 0x02)
Field(\PR22, WordAcc, NoLock, Preserve) {
P22, 16
}
OperationRegion(\PR30, SystemIO, 0x1030, 0x02)
Field(\PR30, WordAcc, NoLock, Preserve) {
P30, 16
}
OperationRegion(\PR40, SystemIO, 0x1040, 0x01)
Field(\PR40, ByteAcc, NoLock, Preserve) {
P40, 8
}
OperationRegion(\PR42, SystemIO, 0x1042, 0x01)
Field(\PR42, ByteAcc, NoLock, Preserve) {
P42, 8
}
OperationRegion(\PR62, SystemIO, 0x1062, 0x02)
Field(\PR62, ByteAcc, NoLock, Preserve) {
P62, 16
}
OperationRegion(\PR64, SystemIO, 0x1064, 0x02)
Field(\PR64, ByteAcc, NoLock, Preserve) {
P64, 16
}
OperationRegion(\CGPO, SystemIO, 0x103a, 0x03)
Field(\CGPO, ByteAcc, NoLock, Preserve) {
GP00, 1,
GP01, 1,
GP02, 1,
GP03, 1,
GP04, 1,
GP05, 1,
GP06, 1,
GP07, 1,
GP08, 1,
GP09, 1,
GP0A, 1,
GP0B, 1,
GP0C, 1,
GP0D, 1,
GP0E, 1,
GP0F, 1
}
Scope(\) {
Name(PICF, 0x00)
Method(_PIC, 1) {
Store(Arg0, PICF)
}
}
Name(OSFX, 0x01)
Name(OSFL, 0x01)
Method(STRC, 2) {
If(LNot(LEqual(SizeOf(Arg0), SizeOf(Arg1)))) {
Return(0x00)
}
Add(SizeOf(Arg0), 0x01, Local0)
Name(BUF0, Buffer(Local0) { })
Name(BUF1, Buffer(Local0) { })
Store(Arg0, BUF0)
Store(Arg1, BUF1)
While(Local0) {
Decrement(Local0)
If(LNot(LEqual(DerefOf(Index(BUF0, Local0, )), DerefOf(Index(BUF1, Local0, ))))) {
Return(Zero)
}
}
Return(One)
}
OperationRegion(RTCM, SystemIO, 0x70, 0x02)
Field(RTCM, ByteAcc, NoLock, Preserve) {
CMIN, 8,
CMDA, 8
}
IndexField(CMIN, CMDA, ByteAcc, NoLock, Preserve) {
Offset(0xf),
SHUT, 8
}
OperationRegion(INFO, SystemMemory, 0x000ff840, 0x01)
Field(INFO, ByteAcc, NoLock, Preserve) {
KBDI, 1,
RTCW, 1,
PS2F, 1,
IRFL, 2,
DISE, 1,
SSHU, 1
}
OperationRegion(BEEP, SystemIO, 0x61, 0x01)
Field(BEEP, ByteAcc, NoLock, Preserve) {
S1B, 8
}
OperationRegion(CONT, SystemIO, 0x40, 0x04)
Field(CONT, ByteAcc, NoLock, Preserve) {
CNT0, 8,
CNT1, 8,
CNT2, 8,
CTRL, 8
}
Method(SPKR, 1) {
Store(S1B, Local0)
Store(0xb6, CTRL)
Store(0x55, CNT2)
Store(0x03, CNT2)
Store(Arg0, Local2)
While(LGreater(Local2, 0x00)) {
Or(S1B, 0x03, S1B)
Store(0x5fff, Local3)
While(LGreater(Local3, 0x00)) {
Decrement(Local3)
}
And(S1B, 0xfc, S1B)
Store(0x0eff, Local3)
While(LGreater(Local3, 0x00)) {
Decrement(Local3)
}
Decrement(Local2)
}
Store(Local0, S1B)
}
Method(\_PTS, 1) {
Store(0xff, P1)
If(LEqual(Arg0, 0x03)) {
Store(Arg0, P48)
}
And(P64, Not(0x4000, ), P64)
And(P62, Not(0xc0, ), P62)
If(LEqual(Arg0, 0x01)) {
Or(P62, 0x40, P62)
Or(P64, 0x4000, P64)
}
If(LEqual(Arg0, 0x03)) {
Or(P62, 0x40, P62)
And(P64, Not(0x4000, ), P64)
}
If(LNot(LLess(Arg0, 0x04))) {
Or(P62, 0x80, P62)
Or(P64, 0x4000, P64)
}
Store(0xffff, P20)
Store(0xffff, P30)
Or(Arg0, 0xf0, DBG1)
}
Method(\_WAK, 1) {
If(LEqual(Arg0, 0x04)) {
If(LEqual(OSFL, 0x00)) {
Store(0x58, P48)
}
If(LEqual(OSFL, 0x02)) {
Store(0x57, P48)
}
If(LEqual(OSFL, 0x01)) {
Store(0x56, P48)
}
}
If(LEqual(Arg0, 0x03)) {
Notify(\_SB.PCI0.USB0, 0x00)
Notify(\_SB.PCI0.USB1, 0x00)
Notify(\_SB.PCI0.USB2, 0x00)
Notify(\_SB.PCI0.USB3, 0x00)
}
Store(0xff, DBG1)
And(P62, 0xffbf, P62)
And(P62, 0x40, P62)
Or(P64, 0x4000, P64)
SFAN(0xff)
Store(P40, Local0)
Store(Local0, P40)
If(LEqual(OSFL, 0x01)) {
Notify(\_SB.PWRB, 0x02)
}
Else {
If(LEqual(Arg0, 0x01)) {
And(P1, 0x04, Local0)
If(LEqual(Local0, 0x00)) {
Notify(\_SB.PWRB, 0x02)
}
}
Else {
If(LEqual(RTCW, Zero)) {
Notify(\_SB.PWRB, 0x02)
}
}
}
If(LEqual(Arg0, 0x04)) {
Notify(\_SB.PWRB, 0x02)
}
}
Scope(\_SI) {
Method(_MSG, 1) {
Store(Local0, Local0)
}
Method(_SST, 1) {
Store(Local0, Local0)
}
}
Scope(\_GPE) {
Method(_L00) {
Notify(\_TZ.THRM, 0x80)
}
Method(_L01) {
Notify(\_TZ.THRM, 0x80)
}
Method(_L13) {
Notify(\_SB.FUTS, 0x80)
}
Method(_L0E) {
Notify(\_SB.PCI0.USB0, 0x02)
Notify(\_SB.PWRB, 0x02)
}
Method(_L04) {
Notify(\_SB.PCI0.USB1, 0x02)
Notify(\_SB.PWRB, 0x02)
}
Method(_L07) {
Notify(\_SB.PCI0.USB2, 0x02)
Notify(\_SB.PWRB, 0x02)
}
Method(_L06) {
Notify(\_SB.PCI0.USB3, 0x02)
Notify(\_SB.PWRB, 0x02)
}
Method(_L05) {
Notify(\_SB.PCI0.AMR0, 0x02)
}
Method(_L08) {
Notify(\_SB.PCI0.UAR1, 0x00)
Notify(\_SB.PCI0.UAR2, 0x00)
}
Method(_L0F) {
Notify(\_SB.PCI0.PS2K, 0x00)
Notify(\_SB.PWRB, 0x02)
}
Method(_L0D) {
Notify(\_SB.PCI0.PS2M, 0x00)
Notify(\_SB.PWRB, 0x02)
}
Method(_L0B) {
Notify(\_SB.PCI0, 0x02)
Notify(\_SB.PCI0.PCI1, 0x02)
Notify(\_SB.PCI0.PCI2, 0x02)
Notify(\_SB.PCI0.PCI3, 0x02)
Notify(\_SB.PCI0.PCI4, 0x02)
Notify(\_SB.PCI0.PCI5, 0x02)
}
Method(_L0C) {
Notify(\_SB.PCI0.MAC0, 0x02)
}
}
Scope(\_PR.CPU0) {
Name(_PCT, Package(0x02) {
Buffer(0x11) {0x82, 0xc, 0x0, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x79, 0x0 },
Buffer(0x11) {0x82, 0xc, 0x0, 0x7f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x79, 0x0 },
})
Method(_PPC) {
Return(0x00)
}
Name(_PSS, Package(0x04) {
Package(0x06) {
0x0898,
0x00015ba8,
0x64,
0x09,
0xe020288e,
0x008e,
},
Package(0x06) {
0x07d0,
0x00010d88,
0x64,
0x09,
0xe020298c,
0x018c,
},
Package(0x06) {
0x0708,
0x0000c350,
0x64,
0x09,
0xe0202a8a,
0x028a,
},
Package(0x06) {
0x03e8,
0x000055f0,
0x64,
0x09,
0xe0202c82,
0x0482,
},
Package(0x06) {
0xffff,
0xffffffff,
0xff,
0xff,
0xffffffff,
0x03ff,
},
Package(0x06) {
0xffff,
0xffffffff,
0xff,
0xff,
0xffffffff,
0x03ff,
},
})
}
Scope(\_SB) {
Device(PWRB) {
Name(_HID, 0x0c0cd041)
Method(_STA) {
Return(0x0b)
}
}
Device(FUTS) {
Name(_HID, 0x0e0cd041)
Method(_STA) {
Return(0x0b)
}
}
Device(MEM) {
Name(_HID, 0x010cd041)
Method(_CRS) {
Name(BUF0, Buffer(0x92) {0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0xf, 0x0, 0x0, 0x40, 0x0, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x40, 0xf, 0x0, 0x0, 0x40, 0x0, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x80, 0xf, 0x0, 0x0, 0x40, 0x0, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0xc0, 0xf, 0x0, 0x0, 0x40, 0x0, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0xff, 0xff, 0x0, 0x0, 0x1, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0xee, 0xff, 0x0, 0x0, 0x2, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0xfe, 0xff, 0x0, 0x0, 0x1, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0xc0, 0xfe, 0x0, 0x0, 0x10, 0x0, 0x86, 0x9, 0x0, 0x1, 0x0, 0x0, 0xe0, 0xfe, 0x0, 0x0, 0x10, 0x0, 0x79, 0x0 })
CreateDWordField(BUF0, 0x34, ACMM)
CreateDWordField(BUF0, 0x04, RMA1)
CreateDWordField(BUF0, 0x08, RSS1)
CreateDWordField(BUF0, 0x10, RMA2)
CreateDWordField(BUF0, 0x14, RSS2)
CreateDWordField(BUF0, 0x1c, RMA3)
CreateDWordField(BUF0, 0x20, RSS3)
CreateDWordField(BUF0, 0x28, RMA4)
CreateDWordField(BUF0, 0x2c, RSS4)
CreateDWordField(BUF0, 0x5c, EXTM)
Subtract(AMEM, 0x00100000, EXTM)
If(LNot(LEqual(ROM1, Zero))) {
Store(RMA1, RMA2)
ShiftLeft(ROM1, 0x08, Local0)
Store(Local0, RMA1)
ShiftLeft(RMS1, 0x08, Local0)
Store(Local0, RSS1)
Store(0x8000, RSS2)
}
If(LNot(LEqual(ROM2, Zero))) {
Store(RMA2, RMA3)
ShiftLeft(ROM2, 0x08, Local0)
Store(Local0, RMA2)
ShiftLeft(RMS2, 0x08, Local0)
Store(Local0, RSS2)
Store(0xc000, RSS3)
}
If(LNot(LEqual(ROM3, Zero))) {
Store(RMA3, RMA4)
ShiftLeft(ROM3, 0x08, Local0)
Store(Local0, RMA3)
ShiftLeft(RMS3, 0x08, Local0)
Store(Local0, RSS3)
Store(0x00010000, RSS4)
}
Store(AMEM, ACMM)
Return(BUF0)
}
}
Device(PCI0) {
Name(_HID, 0x030ad041)
Name(_ADR, 0x00)
Method(SS3D) {
If(LEqual(OSFL, 0x02)) {
Return(0x02)
}
Else {
Return(0x03)
}
}
Device(IDEC) {
Name(_ADR, 0x00020005)
Name(IO5T, Package(0x03) {
Package(0x07) {
0x78,
0xb4,
0x014a,
0x0186,
0x0258,
0x78,
0x96,
},
Package(0x07) {
0x06,
0x07,
0x1c,
0x1c,
0x1c,
0x06,
0x07,
},
Package(0x07) {
0x04,
0x09,
0x03,
0x09,
0x1e,
0x04,
0x06,
},
})
Name(IO6T, Package(0x03) {
Package(0x07) {
0x78,
0xb4,
0x014a,
0x0186,
0x0258,
0x78,
0xb4,
},
Package(0x07) {
0x09,
0x0a,
0x26,
0x26,
0x26,
0x09,
0x0a,
},
Package(0x07) {
0x05,
0x0c,
0x04,
0x0c,
0x28,
0x05,
0x0c,
},
})
Name(UM5T, Package(0x06) {
0x0b,
0x07,
0x05,
0x04,
0x02,
0x01,
})
Name(UM6T, Package(0x07) {
0x0f,
0x0a,
0x07,
0x05,
0x03,
0x02,
0x01,
})
Name(PIO5, Package(0x05) {
0x3a,
0x25,
0x1f,
0x10,
0x0a,
})
Name(PIO6, Package(0x05) {
0x4e,
0x32,
0x2a,
0x16,
0x0e,
})
Name(CRCT, Package(0x07) {
0x06,
0x04,
0x03,
0x01,
0x01,
0x01,
0x01,
})
Name(INTT, Package(0x05) {
0x02,
0x02,
0x02,
0x04,
0x06,
})
Name(DMAT, Package(0x05) {
0x00,
0x01,
0x01,
0x01,
0x02,
})
Name(RMFL, 0x01)
OperationRegion(CF40, PCI_Config, 0x40, 0x18)
Field(CF40, WordAcc, NoLock, Preserve) {
, 1,
IOR0, 1,
UDM0, 1,
UM60, 1,
UCT0, 4,
CRC0, 4,
INI0, 4,
ATT0, 6,
Offset(0x3),
RCT0, 6,
Offset(0x4),
, 1,
IOR1, 1,
UDM1, 1,
UM61, 1,
UCT1, 4,
CRC1, 4,
INI1, 4,
ATT1, 6,
Offset(0x7),
RCT1, 6,
Offset(0x8),
, 1,
IOR2, 1,
UDM2, 1,
UM62, 1,
UCT2, 4,
CRC2, 4,
INI2, 4,
ATT2, 6,
Offset(0xb),
RCT2, 6,
Offset(0xc),
, 1,
IOR3, 1,
UDM3, 1,
UM63, 1,
UCT3, 4,
CRC3, 4,
INI3, 4,
ATT3, 6,
Offset(0xf),
RCT3, 6,
Offset(0x10),
, 1,
CHE0, 1,
Offset(0x12),
, 1,
CHE1, 1,
Offset(0x14),
, 30,
REMP, 1,
Offset(0x18)
}
Name(IDEP, Buffer(0x14) { })
CreateDWordField(IDEP, 0x00, GTM0)
CreateDWordField(IDEP, 0x04, GTM1)
CreateDWordField(IDEP, 0x08, GTM2)
CreateDWordField(IDEP, 0x0c, GTM3)
CreateDWordField(IDEP, 0x10, GTM4)
Device(IDE0) {
Name(_ADR, 0x00)
Method(_GTM) {
Store(0xffffffff, Local0)
Store(0xffffffff, Local1)
Store(0xffffffff, Local2)
Store(0xffffffff, Local3)
Store(0x10, Local4)
Store(REMP, RMFL)
Store(0x00, REMP)
If(CHE0) {
If(LNot(LEqual(ATT0, 0x00))) {
Add(RCT0, 0x01, Local5)
Add(ATT0, 0x01, Local6)
Add(Local5, Local6, Local5)
Multiply(UM60, 0x05, Local6)
Subtract(0x14, Local6, Local7)
Multiply(Local5, Local7, Local0)
ShiftRight(Local0, 0x01, Local0)
If(LNot(LGreater(Local0, 0xb4))) {
Store(Local0, Local1)
}
If(IOR0) {
Or(Local4, 0x02, Local4)
}
If(UDM0) {
Add(UCT0, 0x01, Local5)
Multiply(Local5, Local7, Local6)
ShiftRight(Local6, 0x01, Local1)
Or(Local4, 0x01, Local4)
}
}
If(LNot(LEqual(ATT1, 0x00))) {
Add(RCT1, 0x01, Local5)
Add(ATT1, 0x01, Local6)
Add(Local5, Local6, Local5)
Multiply(UM61, 0x05, Local6)
Subtract(0x14, Local6, Local7)
Multiply(Local5, Local7, Local2)
ShiftRight(Local2, 0x01, Local2)
If(LNot(LGreater(Local2, 0xb4))) {
Store(Local2, Local3)
}
If(IOR1) {
Or(Local4, 0x08, Local4)
}
If(UDM1) {
Add(UCT1, 0x01, Local5)
Multiply(Local5, Local7, Local6)
ShiftRight(Local6, 0x01, Local3)
Or(Local4, 0x04, Local4)
}
}
}
Store(RMFL, REMP)
Store(Local0, GTM0)
If(And(P6, 0x80, )) {
Store(0xffffffff, GTM1)
}
Else {
Store(Local1, GTM1)
}
Store(Local2, GTM2)
If(And(P6, 0x40, )) {
Store(0xffffffff, GTM3)
}
Else {
Store(Local3, GTM3)
}
Store(Local4, GTM4)
Return(IDEP)
}
Method(_STM, 3) {
Store(Arg0, IDEP)
Store(GTM0, Local0)
Store(GTM1, Local1)
Store(GTM2, Local2)
Store(GTM3, Local3)
Store(GTM4, Local4)
Store(REMP, RMFL)
Store(0x00, REMP)
If(LAnd(LNot(LEqual(Local1, 0xffffffff)), LNot(LEqual(Local1, 0x00)))) {
If(And(Local4, 0x01, )) {
Store(0x01, UDM0)
If(LLess(Local1, 0x14)) {
Store(0x01, UM60)
Store(0x01, UCT0)
}
Else {
Store(0x00, UM60)
Divide(Local1, 0x0a, Local6, Local5)
Decrement(Local5)
Store(Local5, UCT0)
Store(Match(UM5T, MEQ, Local5, MTR, 0x00, 0x00), Local5)
Store(DerefOf(Index(CRCT, Local5, )), CRC0)
}
}
}
If(LAnd(LNot(LEqual(Local0, 0xffffffff)), LNot(LEqual(Local0, 0x00)))) {
If(UM60) {
Store(Match(DerefOf(Index(IO6T, 0x00, )), MEQ, Local0, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x01, )), Local6, )), ATT0)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x02, )), Local6, )), RCT0)
}
Else {
Store(Match(DerefOf(Index(IO5T, 0x00, )), MEQ, Local0, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x01, )), Local6, )), ATT0)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x02, )), Local6, )), RCT0)
Store(DerefOf(Index(INTT, Local6, )), INI0)
}
}
If(LAnd(LNot(LEqual(Local3, 0xffffffff)), LNot(LEqual(Local3, 0x00)))) {
If(And(Local4, 0x04, )) {
Store(0x01, UDM1)
If(LLess(Local3, 0x14)) {
Store(0x01, UM61)
Store(0x01, UCT1)
}
Else {
Store(0x00, UM61)
Divide(Local3, 0x0a, Local6, Local5)
Decrement(Local5)
Store(Local5, UCT1)
Store(Match(UM5T, MEQ, Local5, MTR, 0x00, 0x00), Local5)
Store(DerefOf(Index(CRCT, Local5, )), CRC1)
}
}
}
If(LAnd(LNot(LEqual(Local2, 0xffffffff)), LNot(LEqual(Local2, 0x00)))) {
If(UM61) {
Store(Match(DerefOf(Index(IO6T, 0x00, )), MEQ, Local2, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x01, )), Local6, )), ATT1)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x02, )), Local6, )), RCT1)
}
Else {
Store(Match(DerefOf(Index(IO5T, 0x00, )), MEQ, Local2, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x01, )), Local6, )), ATT1)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x02, )), Local6, )), RCT1)
Store(DerefOf(Index(INTT, Local6, )), INI1)
}
}
Store(RMFL, REMP)
}
Device(DRV0) {
Name(_ADR, 0x00)
Method(_GTF) {
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef }, Local6)
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef }, Local7)
CreateByteField(Local6, 0x01, MODE)
CreateByteField(Local7, 0x01, UMOD)
Store(REMP, RMFL)
Store(0x00, REMP)
If(LNot(LEqual(ATT0, 0x00))) {
Add(ATT0, RCT0, Local5)
If(UM60) {
Store(Match(PIO6, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
Else {
Store(Match(PIO5, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
If(UDM0) {
If(UM60) {
Store(Match(UM6T, MEQ, UCT0, MTR, 0x00, 0x00), UMOD)
}
Else {
Store(Match(UM5T, MEQ, UCT0, MTR, 0x00, 0x00), UMOD)
}
Or(UMOD, 0x40, UMOD)
}
Else {
Store(DerefOf(Index(DMAT, MODE, )), UMOD)
Or(UMOD, 0x20, UMOD)
}
Or(MODE, 0x08, MODE)
}
Store(RMFL, REMP)
Concatenate(Local6, Local7, Local5)
Return(Local5)
}
}
Device(DRV1) {
Name(_ADR, 0x01)
Method(_GTF) {
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef }, Local6)
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef }, Local7)
CreateByteField(Local6, 0x01, MODE)
CreateByteField(Local7, 0x01, UMOD)
Store(REMP, RMFL)
Store(0x00, REMP)
If(LNot(LEqual(ATT1, 0x00))) {
Add(ATT1, RCT1, Local5)
If(UM61) {
Store(Match(PIO6, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
Else {
Store(Match(PIO5, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
If(UDM1) {
If(UM61) {
Store(Match(UM6T, MEQ, UCT1, MTR, 0x00, 0x00), UMOD)
}
Else {
Store(Match(UM5T, MEQ, UCT1, MTR, 0x00, 0x00), UMOD)
}
Or(UMOD, 0x40, UMOD)
}
Else {
Store(DerefOf(Index(DMAT, MODE, )), UMOD)
Or(UMOD, 0x20, UMOD)
}
Or(MODE, 0x08, MODE)
}
Store(RMFL, REMP)
Concatenate(Local6, Local7, Local5)
Return(Local5)
}
}
}
Device(IDE1) {
Name(_ADR, 0x01)
Method(_GTM) {
Store(0xffffffff, Local0)
Store(0xffffffff, Local1)
Store(0xffffffff, Local2)
Store(0xffffffff, Local3)
Store(0x10, Local4)
Store(REMP, RMFL)
Store(0x00, REMP)
If(CHE1) {
If(LNot(LEqual(ATT2, 0x00))) {
Add(RCT2, 0x01, Local5)
Add(ATT2, 0x01, Local6)
Add(Local5, Local6, Local5)
Multiply(UM62, 0x05, Local6)
Subtract(0x14, Local6, Local7)
Multiply(Local5, Local7, Local0)
ShiftRight(Local0, 0x01, Local0)
If(LNot(LGreater(Local0, 0xb4))) {
Store(Local0, Local1)
}
If(IOR2) {
Or(Local4, 0x02, Local4)
}
If(UDM2) {
Add(UCT2, 0x01, Local5)
Multiply(Local5, Local7, Local6)
ShiftRight(Local6, 0x01, Local1)
Or(Local4, 0x01, Local4)
}
}
If(LNot(LEqual(ATT3, 0x00))) {
Add(RCT3, 0x01, Local5)
Add(ATT3, 0x01, Local6)
Add(Local5, Local6, Local5)
Multiply(UM63, 0x05, Local6)
Subtract(0x14, Local6, Local7)
Multiply(Local5, Local7, Local2)
ShiftRight(Local2, 0x01, Local2)
If(LNot(LGreater(Local2, 0xb4))) {
Store(Local2, Local3)
}
If(IOR3) {
Or(Local4, 0x08, Local4)
}
If(UDM3) {
Add(UCT3, 0x01, Local5)
Multiply(Local5, Local7, Local6)
ShiftRight(Local6, 0x01, Local3)
Or(Local4, 0x04, Local4)
}
}
}
Store(RMFL, REMP)
Store(Local0, GTM0)
If(And(P6, 0x20, )) {
Store(0xffffffff, GTM1)
}
Else {
Store(Local1, GTM1)
}
Store(Local2, GTM2)
If(And(P6, 0x10, )) {
Store(0xffffffff, GTM3)
}
Else {
Store(Local3, GTM3)
}
Store(Local4, GTM4)
Return(IDEP)
}
Method(_STM, 3) {
Store(Arg0, IDEP)
Store(GTM0, Local0)
Store(GTM1, Local1)
Store(GTM2, Local2)
Store(GTM3, Local3)
Store(GTM4, Local4)
Store(REMP, RMFL)
Store(0x00, REMP)
If(LAnd(LNot(LEqual(Local1, 0xffffffff)), LNot(LEqual(Local1, 0x00)))) {
If(And(Local4, 0x01, )) {
Store(0x01, UDM2)
If(LLess(Local1, 0x14)) {
Store(0x01, UM62)
Store(0x01, UCT2)
}
Else {
Store(0x00, UM62)
Divide(Local1, 0x0a, Local6, Local5)
Decrement(Local5)
Store(Local5, UCT2)
Store(Match(UM5T, MEQ, Local5, MTR, 0x00, 0x00), Local5)
Store(DerefOf(Index(CRCT, Local5, )), CRC2)
}
}
}
If(LAnd(LNot(LEqual(Local0, 0xffffffff)), LNot(LEqual(Local0, 0x00)))) {
If(UM62) {
Store(Match(DerefOf(Index(IO6T, 0x00, )), MEQ, Local0, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x01, )), Local6, )), ATT2)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x02, )), Local6, )), RCT2)
}
Else {
Store(Match(DerefOf(Index(IO5T, 0x00, )), MEQ, Local0, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x01, )), Local6, )), ATT2)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x02, )), Local6, )), RCT2)
Store(DerefOf(Index(INTT, Local6, )), INI2)
}
}
If(LAnd(LNot(LEqual(Local3, 0xffffffff)), LNot(LEqual(Local3, 0x00)))) {
If(And(Local4, 0x04, )) {
Store(0x01, UDM3)
If(LLess(Local3, 0x14)) {
Store(0x01, UM63)
Store(0x01, UCT3)
}
Else {
Store(0x00, UM63)
Divide(Local3, 0x0a, Local6, Local5)
Decrement(Local5)
Store(Local5, UCT3)
Store(Match(UM5T, MEQ, Local5, MTR, 0x00, 0x00), Local5)
Store(DerefOf(Index(CRCT, Local5, )), CRC3)
}
}
}
If(LAnd(LNot(LEqual(Local2, 0xffffffff)), LNot(LEqual(Local2, 0x00)))) {
If(UM63) {
Store(Match(DerefOf(Index(IO6T, 0x00, )), MEQ, Local2, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x01, )), Local6, )), ATT3)
Store(DerefOf(Index(DerefOf(Index(IO6T, 0x02, )), Local6, )), RCT3)
}
Else {
Store(Match(DerefOf(Index(IO5T, 0x00, )), MEQ, Local2, MTR, 0x00, 0x00), Local6)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x01, )), Local6, )), ATT3)
Store(DerefOf(Index(DerefOf(Index(IO5T, 0x02, )), Local6, )), RCT3)
Store(DerefOf(Index(INTT, Local6, )), INI3)
}
}
Store(RMFL, REMP)
}
Device(DRV0) {
Name(_ADR, 0x00)
Method(_GTF) {
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef }, Local6)
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xa0, 0xef }, Local7)
CreateByteField(Local6, 0x01, MODE)
CreateByteField(Local7, 0x01, UMOD)
Store(REMP, RMFL)
Store(0x00, REMP)
If(LNot(LEqual(ATT2, 0x00))) {
Add(ATT2, RCT2, Local5)
If(UM62) {
Store(Match(PIO6, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
Else {
Store(Match(PIO5, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
If(UDM2) {
If(UM62) {
Store(Match(UM6T, MEQ, UCT2, MTR, 0x00, 0x00), UMOD)
}
Else {
Store(Match(UM5T, MEQ, UCT2, MTR, 0x00, 0x00), UMOD)
}
Or(UMOD, 0x40, UMOD)
}
Else {
Store(DerefOf(Index(DMAT, MODE, )), UMOD)
Or(UMOD, 0x20, UMOD)
}
Or(MODE, 0x08, MODE)
}
Store(RMFL, REMP)
Concatenate(Local6, Local7, Local5)
Return(Local5)
}
}
Device(DRV1) {
Name(_ADR, 0x01)
Method(_GTF) {
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef }, Local6)
Store(Buffer(0x07) {0x3, 0x0, 0x0, 0x0, 0x0, 0xb0, 0xef }, Local7)
CreateByteField(Local6, 0x01, MODE)
CreateByteField(Local7, 0x01, UMOD)
Store(REMP, RMFL)
Store(0x00, REMP)
If(LNot(LEqual(ATT3, 0x00))) {
Add(ATT3, RCT3, Local5)
If(UM63) {
Store(Match(PIO6, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
Else {
Store(Match(PIO5, MEQ, Local5, MTR, 0x00, 0x00), MODE)
}
If(UDM3) {
If(UM63) {
Store(Match(UM6T, MEQ, UCT3, MTR, 0x00, 0x00), UMOD)
}
Else {
Store(Match(UM5T, MEQ, UCT3, MTR, 0x00, 0x00), UMOD)
}
Or(UMOD, 0x40, UMOD)
}
Else {
Store(DerefOf(Index(DMAT, MODE, )), UMOD)
Or(UMOD, 0x20, UMOD)
}
Or(MODE, 0x08, MODE)
}
Store(RMFL, REMP)
Concatenate(Local6, Local7, Local5)
Return(Local5)
}
}
}
}
Method(_CRS) {
Name(BUF0, Buffer(0xa6) {0x88, 0xd, 0x0, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0, 0x0, 0x0, 0x1, 0x47, 0x1, 0xf8, 0xc, 0xf8, 0xc, 0x1, 0x8, 0x88, 0xd, 0x0, 0x1, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x4, 0x0, 0x0, 0x80, 0x4, 0x47, 0x1, 0x80, 0x4, 0x80, 0x4, 0x1, 0x10, 0x88, 0xd, 0x0, 0x1, 0xc, 0x3, 0x0, 0x0, 0x90, 0x4, 0xf7, 0xc, 0x0, 0x0, 0x68, 0x8, 0x88, 0xd, 0x0, 0x1, 0xc, 0x3, 0x0, 0x0, 0x0, 0xd, 0xff, 0xf, 0x0, 0x0, 0x0, 0x3, 0x47, 0x1, 0x0, 0x10, 0x0, 0x10, 0x1, 0xe0, 0x47, 0x1, 0xe0, 0x10, 0xe0, 0x10, 0x1, 0x20, 0x88, 0xd, 0x0, 0x1, 0xc, 0x3, 0x0, 0x0, 0x0, 0x11, 0xff, 0xff, 0x0, 0x0, 0x0, 0xef, 0x87, 0x17, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0x0, 0xff, 0xff, 0xb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x87, 0x17, 0x0, 0x0, 0xc, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10, 0x0, 0xff, 0xff, 0xbf, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf0, 0xff, 0x79, 0x0 })
CreateDWordField(BUF0, 0x94, TCMM)
CreateDWordField(BUF0, 0xa0, TOMM)
Add(AMEM, 0x00010000, TCMM)
Subtract(0xfec00000, TCMM, TOMM)
Return(BUF0)
}
Name(PICM, Package(0x26) {
Package(0x04) {
0x0009ffff,
0x00,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x0009ffff,
0x01,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x0009ffff,
0x02,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x0009ffff,
0x03,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x000affff,
0x00,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x000affff,
0x01,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x000affff,
0x02,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x000affff,
0x03,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x000bffff,
0x00,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x000bffff,
0x01,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x000bffff,
0x02,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x000bffff,
0x03,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x000cffff,
0x00,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x000cffff,
0x01,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x000cffff,
0x02,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x000cffff,
0x03,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x000dffff,
0x00,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x000dffff,
0x01,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x000dffff,
0x02,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x000dffff,
0x03,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x0002ffff,
0x00,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x0002ffff,
0x01,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x0002ffff,
0x02,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x0002ffff,
0x03,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x0003ffff,
0x00,
\_SB.PCI0.LNKE,
0x00,
},
Package(0x04) {
0x0003ffff,
0x01,
\_SB.PCI0.LNKF,
0x00,
},
Package(0x04) {
0x0003ffff,
0x02,
\_SB.PCI0.LNKG,
0x00,
},
Package(0x04) {
0x0003ffff,
0x03,
\_SB.PCI0.LNKH,
0x00,
},
Package(0x04) {
0x0004ffff,
0x00,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x0004ffff,
0x01,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x0004ffff,
0x02,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x0004ffff,
0x03,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x0005ffff,
0x00,
\_SB.PCI0.LNKB,
0x00,
},
Package(0x04) {
0x0005ffff,
0x01,
\_SB.PCI0.LNKC,
0x00,
},
Package(0x04) {
0x0005ffff,
0x02,
\_SB.PCI0.LNKD,
0x00,
},
Package(0x04) {
0x0005ffff,
0x03,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x0001ffff,
0x00,
\_SB.PCI0.LNKA,
0x00,
},
Package(0x04) {
0x0001ffff,
0x01,
\_SB.PCI0.LNKB,
0x00,
},
})
Name(APIC, Package(0x26) {
Package(0x04) {
0x0009ffff,
0x00,
0x00,
0x11,
},
Package(0x04) {
0x0009ffff,
0x01,
0x00,
0x12,
},
Package(0x04) {
0x0009ffff,
0x02,
0x00,
0x13,
},
Package(0x04) {
0x0009ffff,
0x03,
0x00,
0x10,
},
Package(0x04) {
0x000affff,
0x00,
0x00,
0x12,
},
Package(0x04) {
0x000affff,
0x01,
0x00,
0x13,
},
Package(0x04) {
0x000affff,
0x02,
0x00,
0x10,
},
Package(0x04) {
0x000affff,
0x03,
0x00,
0x11,
},
Package(0x04) {
0x000bffff,
0x00,
0x00,
0x11,
},
Package(0x04) {
0x000bffff,
0x01,
0x00,
0x12,
},
Package(0x04) {
0x000bffff,
0x02,
0x00,
0x13,
},
Package(0x04) {
0x000bffff,
0x03,
0x00,
0x10,
},
Package(0x04) {
0x000cffff,
0x00,
0x00,
0x10,
},
Package(0x04) {
0x000cffff,
0x01,
0x00,
0x11,
},
Package(0x04) {
0x000cffff,
0x02,
0x00,
0x12,
},
Package(0x04) {
0x000cffff,
0x03,
0x00,
0x13,
},
Package(0x04) {
0x000dffff,
0x00,
0x00,
0x13,
},
Package(0x04) {
0x000dffff,
0x01,
0x00,
0x10,
},
Package(0x04) {
0x000dffff,
0x02,
0x00,
0x11,
},
Package(0x04) {
0x000dffff,
0x03,
0x00,
0x12,
},
Package(0x04) {
0x0002ffff,
0x00,
0x00,
0x10,
},
Package(0x04) {
0x0002ffff,
0x01,
0x00,
0x11,
},
Package(0x04) {
0x0002ffff,
0x02,
0x00,
0x12,
},
Package(0x04) {
0x0002ffff,
0x03,
0x00,
0x13,
},
Package(0x04) {
0x0003ffff,
0x00,
0x00,
0x14,
},
Package(0x04) {
0x0003ffff,
0x01,
0x00,
0x15,
},
Package(0x04) {
0x0003ffff,
0x02,
0x00,
0x16,
},
Package(0x04) {
0x0003ffff,
0x03,
0x00,
0x17,
},
Package(0x04) {
0x0004ffff,
0x00,
0x00,
0x13,
},
Package(0x04) {
0x0004ffff,
0x01,
0x00,
0x10,
},
Package(0x04) {
0x0004ffff,
0x02,
0x00,
0x11,
},
Package(0x04) {
0x0004ffff,
0x03,
0x00,
0x12,
},
Package(0x04) {
0x0005ffff,
0x00,
0x00,
0x11,
},
Package(0x04) {
0x0005ffff,
0x01,
0x00,
0x12,
},
Package(0x04) {
0x0005ffff,
0x02,
0x00,
0x13,
},
Package(0x04) {
0x0005ffff,
0x03,
0x00,
0x10,
},
Package(0x04) {
0x0001ffff,
0x00,
0x00,
0x10,
},
Package(0x04) {
0x0001ffff,
0x01,
0x00,
0x11,
},
})
Method(_PRT) {
If(LNot(PICF)) {
Return(PICM)
}
Else {
Return(APIC)
}
}
Device(PCI1) {
Name(_BBN, 0x00)
Name(_ADR, 0x0009ffff)
}
Device(PCI2) {
Name(_BBN, 0x00)
Name(_ADR, 0x000affff)
}
Device(PCI3) {
Name(_BBN, 0x00)
Name(_ADR, 0x000bffff)
}
Device(PCI4) {
Name(_BBN, 0x00)
Name(_ADR, 0x000cffff)
}
Device(PCI5) {
Name(_BBN, 0x00)
Name(_ADR, 0x000dffff)
}
Device(S962) {
Name(_ADR, 0x00020000)
OperationRegion(PIRQ, PCI_Config, 0x41, 0x04)
Scope(\) {
Field(\_SB.PCI0.S962.PIRQ, ByteAcc, NoLock, Preserve) {
PIRA, 8,
PIRB, 8,
PIRC, 8,
PIRD, 8
}
}
OperationRegion(PIR2, PCI_Config, 0x60, 0x04)
Scope(\) {
Field(\_SB.PCI0.S962.PIR2, ByteAcc, NoLock, Preserve) {
PIRE, 8,
PIRF, 8,
PIRG, 8,
PIRH, 8
}
}
OperationRegion(APCE, PCI_Config, 0x48, 0x01)
Scope(\) {
Field(\_SB.PCI0.S962.APCE, ByteAcc, NoLock, Preserve) {
APC0, 8
}
}
OperationRegion(VERG, PCI_Config, 0xf0, 0x01)
Scope(\) {
Field(\_SB.PCI0.S962.VERG, ByteAcc, NoLock, Preserve) {
SBVR, 8
}
}
OperationRegion(PS2M, PCI_Config, 0x47, 0x01)
Scope(\) {
Field(\_SB.PCI0.S962.PS2M, ByteAcc, NoLock, Preserve) {
PS2S, 8
}
}
}
Scope(\) {
Method(DISD, 1) {
}
Method(CKIO, 2) {
}
Method(SLDM, 2) {
}
}
Device(USB0) {
Name(_ADR, 0x00030000)
Method(SS3D) {
If(LEqual(OSFL, 0x02)) {
Return(0x02)
}
Else {
Return(0x03)
}
}
}
Device(USB1) {
Name(_ADR, 0x00030001)
Method(SS3D) {
If(LEqual(OSFL, 0x02)) {
Return(0x02)
}
Else {
Return(0x03)
}
}
}
Device(USB2) {
Name(_ADR, 0x00030002)
Method(SS3D) {
If(LEqual(OSFL, 0x02)) {
Return(0x02)
}
Else {
Return(0x03)
}
}
}
Device(USB3) {
Name(_ADR, 0x00030003)
Method(SS3D) {
If(LEqual(OSFL, 0x02)) {
Return(0x02)
}
Else {
Return(0x03)
}
}
}
Device(MAC0) {
Name(_ADR, 0x00040000)
}
Device(AUD0) {
Name(_ADR, 0x00020007)
}
Device(AMR0) {
Name(_ADR, 0x00020006)
}
Device(SATA) {
Name(_ADR, 0x00050000)
}
Name(BUFA, Buffer(0x06) {0x23, 0xf8, 0xde, 0x18, 0x79, 0x0 })
Name(BUFB, Buffer(0x06) {0x23, 0x0, 0x0, 0x18, 0x79, 0x0 })
CreateWordField(BUFB, 0x01, IRQV)
Device(LNKA) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x01)
Method(_STA) {
And(PIRA, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRA, 0x80, PIRA)
}
Method(_CRS) {
And(PIRA, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRA)
}
}
Device(LNKB) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x02)
Method(_STA) {
And(PIRB, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRB, 0x80, PIRB)
}
Method(_CRS) {
And(PIRB, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRB)
}
}
Device(LNKC) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x03)
Method(_STA) {
And(PIRC, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRC, 0x80, PIRC)
}
Method(_CRS) {
And(PIRC, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRC)
}
}
Device(LNKD) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x04)
Method(_STA) {
And(PIRD, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRD, 0x80, PIRD)
}
Method(_CRS) {
And(PIRD, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRD)
}
}
Device(LNKE) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x05)
Method(_STA) {
And(PIRE, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRE, 0x80, PIRE)
}
Method(_CRS) {
And(PIRE, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRE)
}
}
Device(LNKF) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x06)
Method(_STA) {
And(PIRF, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRF, 0x80, PIRF)
}
Method(_CRS) {
And(PIRF, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRF)
}
}
Device(LNKG) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x07)
Method(_STA) {
And(PIRG, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRG, 0x80, PIRG)
}
Method(_CRS) {
And(PIRG, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRG)
}
}
Device(LNKH) {
Name(_HID, 0x0f0cd041)
Name(_UID, 0x08)
Method(_STA) {
And(PIRH, 0x80, Local0)
If(LEqual(Local0, 0x80)) {
Return(0x09)
}
Else {
Return(0x0b)
}
}
Method(_PRS) {
Return(BUFA)
}
Method(_DIS) {
Or(PIRH, 0x80, PIRH)
}
Method(_CRS) {
And(PIRH, 0x0f, Local0)
ShiftLeft(0x01, Local0, IRQV)
Return(BUFB)
}
Method(_SRS, 1) {
CreateWordField(Arg0, 0x01, IRQ1)
FindSetRightBit(IRQ1, Local0)
Decrement(Local0)
Store(Local0, PIRH)
}
}
Scope(\) {
OperationRegion(\SCPP, SystemIO, 0x1048, 0x01)
Field(\SCPP, ByteAcc, NoLock, Preserve) {
SMIP, 8
}
}
Method(\_SB.PCI0._INI) {
If(STRC(\_OS, "Microsoft\x20Windows")) {
}
Else {
If(STRC(\_OS, "Microsoft\x20Windows\x20NT")) {
Store(0x58, SMIP)
Store(0x00, OSFX)
Store(0x00, OSFL)
}
Else {
Store(0x02, OSFX)
Store(0x02, OSFL)
}
}
}
Device(SYSR) {
Name(_HID, 0x020cd041)
Name(_UID, 0x01)
Name(_CRS, Buffer(0x62) {0x47, 0x1, 0x10, 0x0, 0x10, 0x0, 0x1, 0x10, 0x47, 0x1, 0x22, 0x0, 0x22, 0x0, 0x1, 0x1e, 0x47, 0x1, 0x44, 0x0, 0x44, 0x0, 0x1, 0x1c, 0x47, 0x1, 0x62, 0x0, 0x62, 0x0, 0x1, 0x2, 0x47, 0x1, 0x65, 0x0, 0x65, 0x0, 0x1, 0xb, 0x47, 0x1, 0x74, 0x0, 0x74, 0x0, 0x1, 0xc, 0x47, 0x1, 0x91, 0x0, 0x91, 0x0, 0x1, 0x3, 0x47, 0x1, 0xa2, 0x0, 0xa2, 0x0, 0x1, 0x1e, 0x47, 0x1, 0xe0, 0x0, 0xe0, 0x0, 0x1, 0x10, 0x47, 0x1, 0xd0, 0x4, 0xd0, 0x4, 0x1, 0x2, 0x47, 0x1, 0x0, 0x8, 0x0, 0x8, 0x1, 0x6, 0x47, 0x1, 0x90, 0x2, 0x90, 0x2, 0x1, 0x8, 0x79, 0x0 })
}
Device(PIC) {
Name(_HID, 0xd041)
Name(_CRS, Buffer(0x15) {0x47, 0x1, 0x20, 0x0, 0x20, 0x0, 0x1, 0x2, 0x47, 0x1, 0xa0, 0x0, 0xa0, 0x0, 0x1, 0x2, 0x22, 0x4, 0x0, 0x79, 0x0 })
}
Device(DMA1) {
Name(_HID, 0x0002d041)
Name(_CRS, Buffer(0x25) {0x2a, 0x10, 0x4, 0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x10, 0x47, 0x1, 0x80, 0x0, 0x80, 0x0, 0x1, 0x11, 0x47, 0x1, 0x94, 0x0, 0x94, 0x0, 0x1, 0xc, 0x47, 0x1, 0xc0, 0x0, 0xc0, 0x0, 0x1, 0x20, 0x79, 0x0 })
}
Device(TMR) {
Name(_HID, 0x0001d041)
Name(_CRS, Buffer(0x0d) {0x47, 0x1, 0x40, 0x0, 0x40, 0x0, 0x1, 0x4, 0x22, 0x1, 0x0, 0x79, 0x0 })
}
Device(RTC) {
Name(_HID, 0x000bd041)
Name(_CRS, Buffer(0x0d) {0x47, 0x1, 0x70, 0x0, 0x70, 0x0, 0x4, 0x4, 0x22, 0x0, 0x1, 0x79, 0x0 })
}
Device(SPKR) {
Name(_HID, 0x0008d041)
Name(_CRS, Buffer(0x0a) {0x47, 0x1, 0x61, 0x0, 0x61, 0x0, 0x1, 0x1, 0x79, 0x0 })
}
Device(COPR) {
Name(_HID, 0x040cd041)
Name(_CRS, Buffer(0x0d) {0x47, 0x1, 0xf0, 0x0, 0xf0, 0x0, 0x1, 0x10, 0x22, 0x0, 0x20, 0x79, 0x0 })
}
Scope(\) {
OperationRegion(WIN1, SystemIO, 0x2e, 0x02)
Field(WIN1, ByteAcc, NoLock, Preserve) {
INDP, 8,
DATP, 8
}
IndexField(INDP, DATP, ByteAcc, NoLock, Preserve) {
Offset(0x2),
CFG, 8,
Offset(0x7),
LDN, 8,
Offset(0x20),
IDHI, 8,
IDLO, 8,
POWC, 8,
Offset(0x30),
ACTR, 8,
Offset(0x60),
IOAH, 8,
IOAL, 8,
IO2H, 8,
IO2L, 8,
Offset(0x70),
INTR, 8,
Offset(0x72),
INT1, 8,
Offset(0x74),
DMCH, 8,
Offset(0xf0),
OPT1, 8,
OPT2, 8,
OPT3, 8
}
Method(ENFG) {
Store(0x87, INDP)
Store(0x01, INDP)
Store(0x55, INDP)
Store(0x55, INDP)
Or(POWC, 0x80, POWC)
}
Method(EXFG) {
Store(0x02, CFG)
}
Method(GSRG, 1) {
Store(Arg0, INDP)
Return(DATP)
}
Method(SSRG, 2) {
Store(Arg0, INDP)
Store(Arg1, DATP)
}
}
Device(FDC0) {
Name(_HID, 0x0007d041)
Method(_STA) {
ENFG()
Store(Zero, LDN)
If(ACTR) {
EXFG()
Return(0x0f)
}
Else {
If(LOr(IOAH, IOAL)) {
EXFG()
Return(0x0d)
}
Else {
EXFG()
Return(0x00)
}
}
}
Method(_DIS) {
ENFG()
Store(0x00, LDN)
XOr(ACTR, 0x01, Local0)
Store(Local0, ACTR)
Store(DMCH, Local1)
ShiftLeft(IOAH, 0x08, Local2)
Or(IOAL, Local2, Local2)
EXFG()
If(LEqual(Local0, 0x00)) {
SLDM(Local1, 0x04)
DISD(0x03)
}
Else {
SLDM(Local1, Local1)
CKIO(Local2, 0x03)
}
}
Method(_CRS) {
Name(BUF0, Buffer(0x18) {0x47, 0x1, 0xf0, 0x3, 0xf0, 0x3, 0x1, 0x6, 0x47, 0x1, 0xf7, 0x3, 0xf7, 0x3, 0x1, 0x1, 0x22, 0x40, 0x0, 0x2a, 0x4, 0x0, 0x79, 0x0 })
CreateByteField(BUF0, 0x02, IOLO)
CreateByteField(BUF0, 0x03, IOHI)
CreateByteField(BUF0, 0x04, IORL)
CreateByteField(BUF0, 0x05, IORH)
ENFG()
EXFG()
Return(BUF0)
}
Name(_PRS, Buffer(0x1a) {0x30, 0x47, 0x1, 0xf0, 0x3, 0xf0, 0x3, 0x1, 0x6, 0x47, 0x1, 0xf7, 0x3, 0xf7, 0x3, 0x1, 0x1, 0x22, 0x40, 0x0, 0x2a, 0x4, 0x0, 0x38, 0x79, 0x0 })
Method(_SRS, 1) {
CreateByteField(Arg0, 0x02, IOLO)
CreateByteField(Arg0, 0x03, IOHI)
CreateWordField(Arg0, 0x02, IOAD)
CreateWordField(Arg0, 0x19, IRQW)
CreateByteField(Arg0, 0x1c, DMAV)
ENFG()
Store(Zero, LDN)
Store(One, ACTR)
SLDM(DMCH, DMCH)
CKIO(IOAD, 0x03)
EXFG()
}
}
Device(UAR1) {
Name(_HID, 0x0105d041)
Name(_UID, 0x01)
Method(_STA) {
ENFG()
Store(0x01, LDN)
If(ACTR) {
EXFG()
Return(0x0f)
}
Else {
If(LOr(IOAH, IOAL)) {
EXFG()
Return(0x0d)
}
Else {
EXFG()
Return(0x00)
}
}
EXFG()
}
Method(_DIS) {
ENFG()
Store(0x01, LDN)
Store(Zero, ACTR)
EXFG()
DISD(0x00)
}
Method(_CRS) {
Name(BUF1, Buffer(0x0d) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x22, 0x0, 0x0, 0x79, 0x0 })
CreateByteField(BUF1, 0x02, IOLO)
CreateByteField(BUF1, 0x03, IOHI)
CreateByteField(BUF1, 0x04, IORL)
CreateByteField(BUF1, 0x05, IORH)
CreateWordField(BUF1, 0x09, IRQW)
ENFG()
Store(0x01, LDN)
Store(IOAL, IOLO)
Store(IOAL, IORL)
Store(IOAH, IOHI)
Store(IOAH, IORH)
Store(One, Local0)
ShiftLeft(Local0, INTR, IRQW)
EXFG()
Return(BUF1)
}
Name(_PRS, Buffer(0x33) {0x30, 0x47, 0x1, 0xf8, 0x3, 0xf8, 0x3, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0xf8, 0x2, 0xf8, 0x2, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0xe8, 0x3, 0xe8, 0x3, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0xe8, 0x2, 0xe8, 0x2, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x38, 0x79, 0x0 })
Method(_SRS, 1) {
CreateByteField(Arg0, 0x02, IOLO)
CreateByteField(Arg0, 0x03, IOHI)
CreateWordField(Arg0, 0x02, IOAD)
CreateWordField(Arg0, 0x09, IRQW)
ENFG()
Store(0x01, LDN)
Store(One, ACTR)
Store(IOLO, IOAL)
Store(IOHI, IOAH)
FindSetRightBit(IRQW, Local0)
Subtract(Local0, 0x01, INTR)
EXFG()
CKIO(IOAD, 0x00)
}
}
Device(UAR2) {
Method(_HID) {
ENFG()
Store(0x02, LDN)
And(OPT2, 0x07, Local0)
If(LEqual(Local0, 0x04)) {
Return(0x05878526)
}
Else {
Return(0x0105d041)
}
EXFG()
}
Name(_UID, 0x02)
Method(_STA) {
ENFG()
Store(0x02, LDN)
And(OPT2, 0x07, Local0)
If(LNot(LEqual(Local0, 0x01))) {
If(ACTR) {
EXFG()
Return(0x0f)
}
Else {
If(LOr(IOAH, IOAL)) {
EXFG()
Return(0x0d)
}
Else {
EXFG()
Return(0x00)
}
}
}
Else {
EXFG()
Return(0x00)
}
}
Method(_DIS) {
ENFG()
Store(0x02, LDN)
Store(Zero, ACTR)
EXFG()
DISD(0x01)
}
Method(_CRS) {
Name(BUF2, Buffer(0x0d) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x22, 0x10, 0x0, 0x79, 0x0 })
CreateByteField(BUF2, 0x02, IOLO)
CreateByteField(BUF2, 0x03, IOHI)
CreateByteField(BUF2, 0x04, IORL)
CreateByteField(BUF2, 0x05, IORH)
CreateWordField(BUF2, 0x09, IRQW)
ENFG()
Store(0x02, LDN)
Store(IOAL, IOLO)
Store(IOAL, IORL)
Store(IOAH, IOHI)
Store(IOAH, IORH)
Store(One, Local0)
ShiftLeft(Local0, INTR, IRQW)
EXFG()
Return(BUF2)
}
Name(_PRS, Buffer(0x33) {0x30, 0x47, 0x1, 0xf8, 0x3, 0xf8, 0x3, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0xf8, 0x2, 0xf8, 0x2, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0xe8, 0x3, 0xe8, 0x3, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0xe8, 0x2, 0xe8, 0x2, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x38, 0x79, 0x0 })
Method(_SRS, 1) {
CreateByteField(Arg0, 0x02, IOLO)
CreateByteField(Arg0, 0x03, IOHI)
CreateWordField(Arg0, 0x02, IOAD)
CreateWordField(Arg0, 0x09, IRQW)
ENFG()
Store(0x02, LDN)
Store(One, ACTR)
Store(IOLO, IOAL)
Store(IOHI, IOAH)
FindSetRightBit(IRQW, Local0)
Subtract(Local0, 0x01, INTR)
EXFG()
CKIO(IOAD, 0x01)
}
}
Device(LPT1) {
Name(_HID, 0x0004d041)
Name(_UID, 0x01)
Method(_STA) {
ENFG()
Store(0x03, LDN)
And(OPT1, 0x02, Local0)
If(LNot(LEqual(Local0, 0x02))) {
If(ACTR) {
EXFG()
Return(0x0f)
}
Else {
If(LOr(IOAH, IOAL)) {
EXFG()
Return(0x0d)
}
Else {
EXFG()
Return(0x00)
}
}
}
Else {
EXFG()
Return(0x00)
}
}
Method(_DIS) {
ENFG()
Store(0x03, LDN)
Store(Zero, ACTR)
EXFG()
DISD(0x02)
}
Method(_CRS) {
Name(BUF5, Buffer(0x0d) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x8, 0x22, 0x0, 0x0, 0x79, 0x0 })
CreateByteField(BUF5, 0x02, IOLO)
CreateByteField(BUF5, 0x03, IOHI)
CreateByteField(BUF5, 0x04, IORL)
CreateByteField(BUF5, 0x05, IORH)
CreateByteField(BUF5, 0x07, IOLE)
CreateWordField(BUF5, 0x09, IRQW)
ENFG()
Store(0x03, LDN)
Store(IOAL, IOLO)
Store(IOLO, IORL)
Store(IOAH, IOHI)
Store(IOHI, IORH)
If(LEqual(IOLO, 0xbc)) {
Store(0x04, IOLE)
}
Else {
Store(0x08, IOLE)
}
Store(One, Local0)
Store(INTR, Local5)
ShiftLeft(Local0, Local5, IRQW)
EXFG()
Return(BUF5)
}
Name(_PRS, Buffer(0x27) {0x30, 0x47, 0x1, 0x78, 0x3, 0x78, 0x3, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0x78, 0x2, 0x78, 0x2, 0x1, 0x8, 0x22, 0xb8, 0x1e, 0x30, 0x47, 0x1, 0xbc, 0x3, 0xbc, 0x3, 0x1, 0x4, 0x22, 0xb8, 0x1e, 0x38, 0x79, 0x0 })
Method(_SRS, 1) {
CreateByteField(Arg0, 0x02, IOLO)
CreateByteField(Arg0, 0x03, IOHI)
CreateWordField(Arg0, 0x02, IOAD)
CreateByteField(Arg0, 0x04, IORL)
CreateByteField(Arg0, 0x05, IORH)
CreateWordField(Arg0, 0x09, IRQW)
ENFG()
Store(0x03, LDN)
Store(One, ACTR)
Store(IOLO, IOAL)
Store(IOHI, IOAH)
FindSetLeftBit(IRQW, Local0)
Subtract(Local0, 0x01, Local0)
Store(Local0, INTR)
EXFG()
CKIO(IOAD, 0x02)
}
}
Device(ECP1) {
Name(_HID, 0x0104d041)
Name(_UID, 0x01)
Method(_STA) {
ENFG()
Store(0x03, LDN)
And(OPT1, 0x02, Local0)
If(LEqual(Local0, 0x02)) {
If(ACTR) {
EXFG()
Return(0x0f)
}
Else {
If(LOr(IOAH, IOAL)) {
EXFG()
Return(0x0d)
}
Else {
EXFG()
Return(0x00)
}
}
}
Else {
EXFG()
Return(0x00)
}
}
Method(_DIS) {
ENFG()
Store(0x03, LDN)
Store(Zero, ACTR)
SLDM(DMCH, 0x04)
EXFG()
DISD(0x02)
}
Method(_CRS) {
Name(BUF6, Buffer(0x18) {0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x4, 0x47, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1, 0x4, 0x22, 0x0, 0x0, 0x2a, 0x0, 0x0, 0x79, 0x0 })
CreateByteField(BUF6, 0x02, IOLO)
CreateByteField(BUF6, 0x03, IOHI)
CreateByteField(BUF6, 0x04, IORL)
CreateByteField(BUF6, 0x05, IORH)
CreateByteField(BUF6, 0x07, IOLE)
CreateByteField(BUF6, 0x0a, IOEL)
CreateByteField(BUF6, 0x0b, IOEH)
CreateByteField(BUF6, 0x0c, IOML)
CreateByteField(BUF6, 0x0d, IOMH)
CreateWordField(BUF6, 0x11, IRQW)
CreateByteField(BUF6, 0x14, DMAC)
ENFG()
Store(0x03, LDN)
Store(IOAL, Local2)
Store(Local2, IOLO)
Store(IOAH, Local3)
Store(Local3, IOHI)
Or(Local3, 0x04, Local3)
Store(Local3, IOEH)
Store(Local3, IOMH)
Store(IOLO, IORL)
Store(IOLO, IOEL)
Store(IOLO, IOML)
Store(IOHI, IORH)
If(LEqual(IOLO, 0xbc)) {
Store(0x04, IOLE)
}
Else {
Store(0x08, IOLE)
}
Store(One, Local0)
Store(INTR, Local5)
ShiftLeft(Local0, Local5, IRQW)
Store(One, Local0)
Store(DMCH, Local5)
ShiftLeft(Local0, Local5, DMAC)
EXFG()
Return(BUF6)
}
Name(_PRS, Buffer(0x48) {0x30, 0x47, 0x1, 0x78, 0x3, 0x78, 0x3, 0x0, 0x8, 0x47, 0x1, 0x78, 0x7, 0x78, 0x7, 0x0, 0x4, 0x22, 0xb8, 0x1e, 0x2a, 0xb, 0x0, 0x30, 0x47, 0x1, 0x78, 0x2, 0x78, 0x2, 0x0, 0x8, 0x47, 0x1, 0x78, 0x6, 0x78, 0x6, 0x0, 0x4, 0x22, 0xb8, 0x1e, 0x2a, 0xb, 0x0, 0x30, 0x47, 0x1, 0xbc, 0x3, 0xbc, 0x3, 0x0, 0x4, 0x47, 0x1, 0xbc, 0x7, 0xbc, 0x7, 0x0, 0x4, 0x22, 0xb8, 0x1e, 0x2a, 0xb, 0x0, 0x38, 0x79, 0x0 })
Method(_SRS, 1) {
CreateByteField(Arg0, 0x02, IOLO)
CreateByteField(Arg0, 0x03, IOHI)
CreateWordField(Arg0, 0x02, IOAD)
CreateWordField(Arg0, 0x11, IRQW)
CreateByteField(Arg0, 0x14, DMAC)
ENFG()
Store(0x03, LDN)
Store(One, ACTR)
Store(IOLO, IOAL)
Store(IOHI, IOAH)
FindSetLeftBit(IRQW, Local0)
Subtract(Local0, 0x01, Local0)
Store(Local0, INTR)
FindSetLeftBit(DMAC, Local1)
Store(DMCH, Local0)
Subtract(Local1, 0x01, DMCH)
SLDM(Local0, DMCH)
EXFG()
CKIO(IOAD, 0x02)
}
}
OperationRegion(KBCT, SystemIO, 0x60, 0x05)
Field(KBCT, ByteAcc, NoLock, Preserve) {
P060, 8,
Offset(0x4),
P064, 8
}
Device(PS2M) {
Name(_HID, 0x130fd041)
Method(_STA) {
If(LEqual(PS2F, 0x00)) {
Return(0x0f)
}
Else {
Return(0x00)
}
}
Method(_CRS) {
Name(BUF1, Buffer(0x05) {0x22, 0x0, 0x10, 0x79, 0x0 })
Name(BUF2, Buffer(0x15) {0x47, 0x1, 0x60, 0x0, 0x60, 0x0, 0x1, 0x1, 0x47, 0x1, 0x64, 0x0, 0x64, 0x0, 0x1, 0x1, 0x22, 0x0, 0x10, 0x79, 0x0 })
If(LEqual(KBDI, 0x01)) {
If(LEqual(OSFL, 0x02)) {
Return(BUF1)
}
If(LEqual(OSFL, 0x01)) {
Return(BUF1)
}
Else {
Return(BUF2)
}
}
Else {
Return(BUF1)
}
}
}
Device(PS2K) {
Name(_HID, 0x0303d041)
Name(_CID, 0x0b03d041)
Method(_STA) {
If(LEqual(KBDI, 0x01)) {
Return(0x00)
}
Else {
Return(0x0f)
}
}
Name(_CRS, Buffer(0x15) {0x47, 0x1, 0x60, 0x0, 0x60, 0x0, 0x1, 0x1, 0x47, 0x1, 0x64, 0x0, 0x64, 0x0, 0x1, 0x1, 0x22, 0x2, 0x0, 0x79, 0x0 })
}
Device(PSMR) {
Name(_HID, 0x020cd041)
Name(_UID, 0x03)
Method(_STA) {
If(LEqual(KBDI, 0x00)) {
Return(0x00)
}
If(LEqual(PS2F, 0x00)) {
If(LEqual(OSFL, 0x02)) {
Return(0x0f)
}
If(LEqual(OSFL, 0x01)) {
Return(0x0f)
}
Return(0x00)
}
Return(0x00)
}
Name(_CRS, Buffer(0x12) {0x47, 0x1, 0x60, 0x0, 0x60, 0x0, 0x1, 0x1, 0x47, 0x1, 0x64, 0x0, 0x64, 0x0, 0x1, 0x1, 0x79, 0x0 })
}
Method(\_SB.PCI0._PRW) {
Return(Package(0x02) {
0x0b,
0x05,
})
}
Method(\_SB.PCI0.UAR1._PRW) {
Return(Package(0x02) {
0x08,
0x05,
})
}
Method(\_SB.PCI0.UAR2._PRW) {
Return(Package(0x02) {
0x08,
0x05,
})
}
Method(\_SB.FUTS._PRW) {
Return(Package(0x02) {
0x13,
0x04,
})
}
Method(\_SB.PCI0.USB0._PRW) {
If(LEqual(OSFL, 0x00)) {
Return(Package(0x02) {
0x0e,
0x03,
})
}
If(LEqual(OSFL, 0x01)) {
Return(Package(0x02) {
0x0e,
0x05,
})
}
If(LEqual(OSFL, 0x02)) {
Return(Package(0x02) {
0x0e,
0x05,
})
}
}
Method(\_SB.PCI0.USB1._PRW) {
If(LEqual(OSFL, 0x00)) {
Return(Package(0x02) {
0x04,
0x03,
})
}
If(LEqual(OSFL, 0x01)) {
Return(Package(0x02) {
0x04,
0x05,
})
}
If(LEqual(OSFL, 0x02)) {
Return(Package(0x02) {
0x04,
0x05,
})
}
}
Method(\_SB.PCI0.USB2._PRW) {
If(LEqual(OSFL, 0x00)) {
Return(Package(0x02) {
0x07,
0x03,
})
}
If(LEqual(OSFL, 0x01)) {
Return(Package(0x02) {
0x07,
0x05,
})
}
If(LEqual(OSFL, 0x02)) {
Return(Package(0x02) {
0x07,
0x05,
})
}
}
Method(\_SB.PCI0.USB3._PRW) {
If(LEqual(OSFL, 0x00)) {
Return(Package(0x02) {
0x06,
0x03,
})
}
If(LEqual(OSFL, 0x01)) {
Return(Package(0x02) {
0x06,
0x05,
})
}
If(LEqual(OSFL, 0x02)) {
Return(Package(0x02) {
0x06,
0x05,
})
}
}
Method(\_SB.PCI0.MAC0._PRW) {
Return(Package(0x02) {
0x0c,
0x05,
})
}
Method(\_SB.PCI0.AMR0._PRW) {
Return(Package(0x02) {
0x05,
0x04,
})
}
Method(\_SB.PCI0.PS2M._PRW) {
Return(Package(0x02) {
0x0d,
0x05,
})
}
Method(\_SB.PCI0.PS2K._PRW) {
Return(Package(0x02) {
0x0f,
0x04,
})
}
}
}
OperationRegion(TEMM, SystemMemory, 0x000ff810, 0x0c)
Field(TEMM, WordAcc, NoLock, Preserve) {
TP1H, 16,
TP1L, 16,
TP2H, 16,
TP2L, 16,
TRPC, 16,
SENF, 16
}
Name(TVAR, Buffer(0x05) {0x0, 0x0, 0x0, 0x0, 0x0 })
CreateByteField(TVAR, 0x00, PLCY)
CreateWordField(TVAR, 0x01, CTOS)
CreateWordField(TVAR, 0x03, CTHY)
Name(TBUF, Buffer(0x04) {0x0, 0x0, 0x0, 0x0 })
CreateByteField(TBUF, 0x00, DB00)
CreateByteField(TBUF, 0x01, DB01)
CreateWordField(TBUF, 0x00, DW00)
CreateWordField(TBUF, 0x02, DW01)
CreateDWordField(TBUF, 0x00, DATD)
OperationRegion(IP, SystemIO, 0x0295, 0x02)
Field(IP, ByteAcc, NoLock, Preserve) {
INDX, 8,
DAT0, 8
}
Method(SCFG, 1) {
SBYT(0x40, Arg0)
}
Method(STOS, 3) {
Divide(Arg2, 0x0a, Local0, )
If(LGreater(Local0, 0x0111)) {
Subtract(Local0, 0x0111, Local0)
}
Else {
Subtract(0x0111, Local0, Local0)
Or(Local0, 0x80, Local0)
}
SBYT(0x40, Local0)
}
Method(STHY, 3) {
Divide(Arg2, 0x0a, Local0, )
If(LGreater(Local0, 0x0111)) {
Subtract(Local0, 0x0111, Local0)
}
Else {
Subtract(0x0111, Local0, Local0)
Or(Local0, 0x80, Local0)
}
SBYT(0x41, Local0)
}
Method(RTMP) {
Store(GBYT(0x29), Local0)
FindSetLeftBit(Local0, Local1)
If(LEqual(Local1, 0x08)) {
And(Local0, 0x7f, Local0)
Multiply(Local0, 0x0a, Local0)
Subtract(0x0aac, Local0, Local0)
}
Else {
Multiply(Local0, 0x0a, Local0)
Add(0x0aac, Local0, Local0)
}
If(LEqual(SSHU, 0x01)) {
Return(0x0c3c)
}
Else {
Return(Local0)
}
}
Method(SBYT, 2) {
Store(Arg0, INDX)
Store(Arg1, DAT0)
}
Method(GBYT, 1) {
Store(Arg0, INDX)
Store(DAT0, Local0)
Return(Local0)
}
Method(SFAN, 1) {
And(SENF, 0x02, Local0)
If(LEqual(Local0, Zero)) {
If(LEqual(Arg0, Zero)) {
FOFF()
}
Else {
FON()
}
}
}
Method(FON) {
SBYT(0x14, 0x00)
}
Method(FOFF) {
XOr(0x00, 0x03, Local0)
SBYT(0x14, Local0)
}
Scope(\_TZ) {
Device(FAN) {
Name(_HID, 0x0b0cd041)
Method(_INI) {
Store(TP1H, CTOS)
Store(TP1L, CTHY)
}
}
ThermalZone(THRM) {
Name(_AL0, Package(0x01) {
FAN,
})
Method(_AC0) {
If(Or(PLCY, PLCY, Local7)) {
Return(TP2H)
}
Else {
Return(TP1H)
}
}
Name(_PSL, Package(0x01) {
\_PR.CPU0,
})
Name(_TSP, 0x3c)
Name(_TC1, 0x04)
Name(_TC2, 0x03)
Method(_PSV) {
If(Or(PLCY, PLCY, Local7)) {
Return(TP1H)
}
Else {
Return(TP2H)
}
}
Method(_CRT) {
Return(TRPC)
}
Method(_TMP) {
And(SENF, 0x01, Local6)
If(LEqual(Local6, 0x01)) {
Return(RTMP())
}
Else {
Return(0x0b86)
}
}
Method(_SCP, 1) {
If(Arg0) {
Store(One, PLCY)
}
Else {
Store(Zero, PLCY)
}
Notify(\_TZ.THRM, 0x81)
}
Method(STMP, 2) {
Store(Arg1, DW00)
If(Arg0) {
STHY(DB00, DB01, DW00)
}
Else {
STOS(DB00, DB01, DW00)
}
}
}
}
}
/*
APIC: Length=90, Revision=1, Checksum=190,
OEMID=AWARD, OEM Table ID=AWRDACPI, OEM Revision=0x42302e31,
Creator ID=AWRD, Creator Revision=0x0
*/
--------------------------------------------------------------------------------
>Fix:
Unknown.
>Release-Note:
>Audit-Trail:
State-Changed-From-To: open->feedback
State-Changed-By: jruoho@NetBSD.org
State-Changed-When: Wed, 20 Apr 2011 05:49:54 +0000
State-Changed-Why:
A lot has happened since 4.99.31, including several ACPICA updates.
Can you verify that the problem is still present in the actual 5.X release
or preferably, in -current?
From: List Mail User <track@Plectere.com>
To: gnats-bugs@NetBSD.org
Cc:
Subject: Re: kern/42112 (5.x/-current ACPI hangs machines which worked under 4.x)
Date: Wed, 20 Apr 2011 01:15:46 -0700 (PDT)
The problem remains in -current, at least as late as 5.99.39. I can
check a more recent build later in the week. The problem is identical for
both i386 and amd64 (the MB is a Socket 754 platform).
From: List Mail User <track@Plectere.com>
To: gnats-bugs@NetBSD.org
Cc:
Subject: Re: kern/42112 (5.x/-current ACPI hangs machines which worked under 4.x)
Date: Wed, 20 Apr 2011 02:52:27 -0700 (PDT)
Hmm... I have some running 5.99.41 (i386) with kernel sources
from Dec. 5 2010 and some with 5.99.38 (amd64) from last August - All
still busted as far as ACPI is concerned.
State-Changed-From-To: feedback->open
State-Changed-By: jruoho@NetBSD.org
State-Changed-When: Thu, 21 Apr 2011 04:34:15 +0000
State-Changed-Why:
The problem is still present. Like most of the comparable cases, the culprit
is probably ioapic(4) rather than acpi(4). This will be revisited later.
>Unformatted:
(Contact us)
$NetBSD: query-full-pr,v 1.39 2013/11/01 18:47:49 spz Exp $
$NetBSD: gnats_config.sh,v 1.8 2006/05/07 09:23:38 tsutsui Exp $
Copyright © 1994-2007
The NetBSD Foundation, Inc. ALL RIGHTS RESERVED.
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