NetBSD Problem Report #49076

From ryo_on@yk.rim.or.jp  Tue Aug  5 21:15:38 2014
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Message-Id: <20140805211535.8773B3001C70A@mail.SiriusCloud.jp>
Date: Wed,  6 Aug 2014 06:15:35 +0900 (JST)
From: ryoon@NetBSD.org
Reply-To: ryoon@NetBSD.org
To: gnats-bugs@gnats.NetBSD.org
Subject: USB 3.0 devices are not attached to xhci hubs
X-Send-Pr-Version: 3.95

>Number:         49076
>Category:       kern
>Synopsis:       USB 3.0 devices are not attached to xhci hubs
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    skrll
>State:          closed
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Tue Aug 05 21:20:00 +0000 2014
>Closed-Date:    Sat Apr 30 09:58:08 +0000 2016
>Last-Modified:  Sat Apr 30 09:58:08 +0000 2016
>Originator:     Ryo ONODERA
>Release:        NetBSD 6.99.49
>Organization:

>Environment:


System: NetBSD temp.elements.tetera.org 6.99.49 NetBSD 6.99.49 (NOI915DRM) #0: Wed Aug 6 04:09:12 JST 2014 ryo_on@bismuth.elements.tetera.org:/usr/obj/amd64/sys/arch/amd64/compile/NOI915DRM amd64
Architecture: x86_64
Machine: amd64
>Description:
My machine (Lenovo ThinkStation E32) has ehci and xhci controller.
I have connected my USB 3.0 flash drive to USB 3.0 connector of
the machine, and it is recognized as a child of ehci.

My another machine (Apple MacBook Air early 2014 11-inch) has xhci only.
No USB device is recognized.

>How-To-Repeat:
Enable xhci in kernel config file, and boot with it.
Connect USB 3.0 stick to USB 3.0 connector.

>Fix:

I have no idea.
Please fix this.

>Release-Note:

>Audit-Trail:
From: Ryo ONODERA <ryo_on@yk.rim.or.jp>
To: gnats-bugs@NetBSD.org
Cc: 
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Sat, 16 Aug 2014 22:19:34 +0900 (JST)

 Hi,

 The following patch enables xhci ports on
 "vendor 0x8086 product 0x8c31" (Lenovo ThinkStation E32's)
 and chip on Apple MacBook Air early 2014 11-inch.

 On the MacBook Air, cv_timedwait in xhci_do_command (it is invoked from
 xhci_enable_slot) returns EWOULDBLOCK, and I cannot get working ports.
 So no device is unusable.

 On ThinkStation E32, it works almost fine with my patch.
 And my Fresco Logic xhci (vendor 0x1b73 product 0x1100) also works
 with my patch.

 This patch is inspired from FreeBSD and Linux code.

 Index: sys/dev/pci/xhci_pci.c
 ===================================================================
 RCS file: /cvsroot/src/sys/dev/pci/xhci_pci.c,v
 retrieving revision 1.3
 diff -u -r1.3 xhci_pci.c
 --- sys/dev/pci/xhci_pci.c	29 Mar 2014 19:28:25 -0000	1.3
 +++ sys/dev/pci/xhci_pci.c	16 Aug 2014 12:57:08 -0000
 @@ -86,6 +86,7 @@
  	//const char *vendor;
  	uint32_t hccparams;
  	char intrbuf[PCI_INTRSTR_LEN];
 +	pcireg_t ports_available;

  	sc->sc_dev = self;
  	sc->sc_bus.hci_private = sc;
 @@ -165,6 +166,18 @@
  		    "vendor 0x%04x", PCI_VENDOR(pa->pa_id));
  #endif

 +/*
 + * Intel's xHCI host controller in Panther Point chipset requires
 + * Intel specific register handling to enable ports.
 + */
 +	ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_USB3PRM);
 +	pci_conf_write(pc, tag, PCI_XHCI_INTEL_USB3_PSSEN, ports_available);
 +	ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_USB3_PSSEN);
 +
 +	ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_USB2PRM);
 +	pci_conf_write(pc, tag, PCI_XHCI_INTEL_XUSB2PR, ports_available);
 +	ports_available = pci_conf_read(pc, tag, PCI_XHCI_INTEL_XUSB2PR);
 +
  	err = xhci_init(sc);
  	if (err) {
  		aprint_error_dev(self, "init failed, error=%d\n", err);
 Index: sys/dev/usb/xhcireg.h
 ===================================================================
 RCS file: /cvsroot/src/sys/dev/usb/xhcireg.h,v
 retrieving revision 1.1
 diff -u -r1.1 xhcireg.h
 --- sys/dev/usb/xhcireg.h	14 Sep 2013 00:40:31 -0000	1.1
 +++ sys/dev/usb/xhcireg.h	16 Aug 2014 12:57:08 -0000
 @@ -34,10 +34,15 @@
  #define	PCI_INTERFACE_XHCI	0x30

  #define	PCI_USBREV		0x60	/* RO USB protocol revision */
 -#define	 PCI_USBREV_MASK	0xFF
 -#define	 PCI_USBREV_3_0		0x30	/* USB 3.0 */
 +#define	PCI_USBREV_MASK		0xFF
 +#define	PCI_USBREV_3_0		0x30	/* USB 3.0 */
  #define	PCI_XHCI_FLADJ		0x61	/* RW frame length adjust */

 +#define	PCI_XHCI_INTEL_XUSB2PR	0xD0    /* Intel USB2 Port Routing */
 +#define	PCI_XHCI_INTEL_USB2PRM	0xD4    /* Intel USB2 Port Routing Mask */
 +#define	PCI_XHCI_INTEL_USB3_PSSEN 0xD8  /* Intel USB3 Port SuperSpeed Enable */
 +#define	PCI_XHCI_INTEL_USB3PRM	0xDC    /* Intel USB3 Port Routing Mask */
 +
  /* XHCI capability registers */
  #define XHCI_CAPLENGTH		0x00	/* RO capability */
  #define	XHCI_CAP_CAPLENGTH(x)	((x) & 0xFF)

 --
 Ryo ONODERA // ryo_on@yk.rim.or.jp
 PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3

From: Takahiro HAYASHI <t.hash425@gmail.com>
To: Ryo ONODERA <ryo_on@yk.rim.or.jp>, kern-bug-people@netbsd.org, 
 gnats-bugs@netbsd.org, ryoon@NetBSD.org
Cc: 
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Sun, 17 Aug 2014 02:50:08 +0900

 On 08/16/14 22:39, Ryo ONODERA wrote:
 >>   The following patch enables xhci ports on
 >>   "vendor 0x8086 product 0x8c31" (Lenovo ThinkStation E32's)
 >>   and chip on Apple MacBook Air early 2014 11-inch.
 >>
 >>   On the MacBook Air, cv_timedwait in xhci_do_command (it is invoked from
 >>   xhci_enable_slot) returns EWOULDBLOCK, and I cannot get working ports.
 >>   So no device is unusable.
 >>
 >>   On ThinkStation E32, it works almost fine with my patch.
 >>   And my Fresco Logic xhci (vendor 0x1b73 product 0x1100) also works
 >>   with my patch.
 > This sentense means that my patch does not break Fresco's xhci.

 It should check PCI vendor and product ID of XHCI and
 apply quirk only if chip is PantherPoint or LynxPoint.

 >>   This patch is inspired from FreeBSD and Linux code.

 Same, from FreeBSD.

 >
 > --
 > Ryo ONODERA // ryo_on@yk.rim.or.jp
 > PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3
 >

 -- 
 t-hash

From: Ryo ONODERA <ryo_on@yk.rim.or.jp>
To: gnats-bugs@NetBSD.org
Cc: 
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Mon, 18 Aug 2014 19:11:53 +0900 (JST)

 Hi,

 Here is error message from my Lynx Point-LP machine (MacBook Air early 2014).
 xhci_do_command() in xhci_enable_slot returns timeout.

 xhci0: xhci_open addr 0 depth 1 port 5 speed 2
 xhci0: xhci_do_command input 0x0000000000000000 0x00000000 0x00002400
 uhub_explore: usbd_new_device failed. error=TIMEOUT
 uhub0: device problem, disabling port 5

 Other ports has similar errors.
 And I cannot use any USB devices.

 P.S.
 I have USBVERSBOSE and USB_DEBUG in my kernel config.

 --
 Ryo ONODERA // ryo_on@yk.rim.or.jp
 PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3

From: Ryo ONODERA <ryo_on@yk.rim.or.jp>
To: gnats-bugs@NetBSD.org
Cc: 
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Sun, 31 Aug 2014 15:14:33 +0900 (JST)

 Hi,

 In addition, the following patch enables
 MacBook 2014's Lynx Point-LP's USB 3.0 ports.

 Lynx Point-LP may never enable interrupt pending flag.

 Index: xhci.c
 ===================================================================
 RCS file: /cvsroot/src/sys/dev/usb/xhci.c,v
 retrieving revision 1.20
 diff -u -r1.20 xhci.c
 --- xhci.c	26 Jul 2014 00:17:57 -0000	1.20
 +++ xhci.c	31 Aug 2014 06:09:58 -0000
 @@ -890,9 +890,11 @@

  	iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
  	//device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman);
 +#if 0
  	if ((iman & XHCI_IMAN_INTR_PEND) == 0) {
  		return 0;
  	}
 +#endif
  	xhci_rt_write_4(sc, XHCI_IMAN(0), iman);
  	iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
  	//device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman);

 MacBook have internal non-root hub, and it seems that
 our xhci implementation has no non-root hub support sadly...
 So I cannot confirm the real functionality, but dmesg shows umass(4).
 (MacBook's keyboard is connected to internal non-root hub.)

 --
 Ryo ONODERA // ryo_on@yk.rim.or.jp
 PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3

From: Ryo ONODERA <ryo_on@yk.rim.or.jp>
To: gnats-bugs@NetBSD.org
Cc: 
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Sun, 31 Aug 2014 20:35:52 +0900 (JST)

 Hi,

 Here is my trial to handle quirks like AHCI
 and taking controller function that enable device detection on
 Lenovo ThinkStation E32's Intel Lynx Point chipset xHC from OpenBSD.

 http://www.netbsd.org/~ryoon/20140831-xhci_for_intel_lynx_point_and_lp.diff

 diff --git a/pci/xhci_pci.c b/pci/xhci_pci.c
 index e4cf9ec..fb2a9ab 100644
 --- a/pci/xhci_pci.c
 +++ b/pci/xhci_pci.c
 @@ -1,4 +1,5 @@
  /*	$NetBSD: xhci_pci.c,v 1.3 2014/03/29 19:28:25 christos Exp $	*/
 +/*	OpenBSD: xhci_pci.c,v 1.4 2014/07/12 17:38:51 yuo Exp	*/

  /*
   * Copyright (c) 1998 The NetBSD Foundation, Inc.
 @@ -43,6 +44,7 @@ __KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.3 2014/03/29 19:28:25 christos Exp $"
  #include <sys/bus.h>

  #include <dev/pci/pcivar.h>
 +#include <dev/pci/pcidevs.h>

  #include <dev/usb/usb.h>
  #include <dev/usb/usbdi.h>
 @@ -52,6 +54,17 @@ __KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.3 2014/03/29 19:28:25 christos Exp $"
  #include <dev/usb/xhcireg.h>
  #include <dev/usb/xhcivar.h>

 +struct xhci_pci_quirk {
 +	pci_vendor_id_t		vendor;
 +	pci_product_id_t	product;
 +	int			quirks;
 +};
 +
 +static const struct xhci_pci_quirk xhci_pci_quirks[] = {
 +	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_XHCI,
 +	    XHCI_QUIRK_FORCE_INTR },
 +};
 +
  struct xhci_pci_softc {
  	struct xhci_softc	sc_xhci;
  	pci_chipset_tag_t	sc_pc;
 @@ -59,6 +72,18 @@ struct xhci_pci_softc {
  };

  static int
 +xhci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
 +{
 +	int i;
 +
 +	for (i = 0; i < __arraycount(xhci_pci_quirks); i++)
 +		if (vendor == xhci_pci_quirks[i].vendor &&
 +		    product == xhci_pci_quirks[i].product)
 +			return xhci_pci_quirks[i].quirks;
 +	return 0;
 +}
 +
 +static int
  xhci_pci_match(device_t parent, cfdata_t match, void *aux)
  {
  	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
 @@ -71,6 +96,76 @@ xhci_pci_match(device_t parent, cfdata_t match, void *aux)
  	return 0;
  }

 +static int
 +xhci_pci_port_route(struct xhci_pci_softc *psc)
 +{
 +	struct xhci_softc * const sc = &psc->sc_xhci;
 +
 +	pcireg_t val;
 +
 +	/*
 +	 * Check USB3 Port Routing Mask register that indicates the ports
 +	 * can be changed from OS, and turn on by USB3 Port SS Enable register.
 +	 */
 +	val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3PRM);
 +	aprint_debug_dev(sc->sc_dev,
 +	    "USB3PRM / USB3.0 configurable ports: 0x%08x\n", val);
 +
 +	pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN, val);
 +	val = pci_conf_read(psc->sc_pc, psc->sc_tag,PCI_XHCI_INTEL_USB3_PSSEN);
 +	aprint_debug_dev(sc->sc_dev,
 +	    "USB3_PSSEN / Enabled USB3.0 ports under xHCI: 0x%08x\n", val);
 +
 +	/*
 +	 * Check USB2 Port Routing Mask register that indicates the USB2.0
 +	 * ports to be controlled by xHCI HC, and switch them to xHCI HC.
 +	 */
 +	val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB2PRM);
 +	aprint_debug_dev(sc->sc_dev,
 +	    "XUSB2PRM / USB2.0 ports can switch from EHCI to xHCI:"
 +	    "0x%08x\n", val);
 +	pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR, val);
 +	val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR);
 +	aprint_debug_dev(sc->sc_dev,
 +	    "XUSB2PR / USB2.0 ports under xHCI: 0x%08x\n", val);
 +
 +	return 0;
 +}
 +
 +static void
 +xhci_pci_takecontroller(struct xhci_pci_softc *psc, int silent)
 +{
 +	uint32_t cparams, xecp, eec;
 +	uint8_t bios_sem;
 +	int i;
 +
 +	cparams = xhci_read_4(&psc->sc_xhci, XHCI_HCCPARAMS);
 +	eec = -1;
 +
 +	/* Synchronise with the BIOS if it owns the controller. */
 +	for (xecp = XHCI_HCC_XECP(cparams) << 2; xecp != 0;
 +	    xecp = XHCI_XECP_NEXT(eec) << 2) {
 +		eec = xhci_read_4(&psc->sc_xhci, xecp);
 +		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
 +			continue;
 +		bios_sem = xhci_read_1(&psc->sc_xhci,
 +		    xecp + XHCI_XECP_BIOS_SEM);
 +		if (bios_sem) {
 +			xhci_write_1(&psc->sc_xhci, xecp + XHCI_XECP_OS_SEM, 1);
 +			aprint_debug("waiting for BIOS to give up control\n");
 +			for (i = 0; i < 5000; i++) {
 +				bios_sem = xhci_read_1(&psc->sc_xhci, xecp +
 +				    XHCI_XECP_BIOS_SEM);
 +			if (bios_sem == 0)
 +				break;
 +			DELAY(1000);
 +			}
 +		if (silent == 0 && bios_sem)
 +			printf("timed out waiting for BIOS\n");
 +		}
 +	}
 +}
 +
  static void
  xhci_pci_attach(device_t parent, device_t self, void *aux)
  {
 @@ -92,6 +187,10 @@ xhci_pci_attach(device_t parent, device_t self, void *aux)

  	pci_aprint_devinfo(pa, "USB Controller");

 +	/* Check for quirks */
 +	sc->sc_xhci_quirks = xhci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
 +						PCI_PRODUCT(pa->pa_id));
 +
  	/* check if memory space access is enabled */
  	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
  #ifdef DEBUG
 @@ -165,12 +264,24 @@ xhci_pci_attach(device_t parent, device_t self, void *aux)
  		    "vendor 0x%04x", PCI_VENDOR(pa->pa_id));
  #endif

 +	/* Take host controller from BIOS */
 +	xhci_pci_takecontroller(psc, 0);
 +
  	err = xhci_init(sc);
  	if (err) {
  		aprint_error_dev(self, "init failed, error=%d\n", err);
  		goto fail;
  	}

 +	/* Intel chipset requires SuperSpeed enable and USB2 port routing */
 +	switch (PCI_VENDOR(pa->pa_id)) {
 +	case PCI_VENDOR_INTEL:
 +		xhci_pci_port_route(psc);
 +		break;
 +	default:
 +		break;
 +	}
 +
  	if (!pmf_device_register1(self, xhci_suspend, xhci_resume,
  	                          xhci_shutdown))
  		aprint_error_dev(self, "couldn't establish power handler\n");
 diff --git a/usb/xhci.c b/usb/xhci.c
 index c13de65..c1cdc07 100644
 --- a/usb/xhci.c
 +++ b/usb/xhci.c
 @@ -209,12 +209,25 @@ static const struct usbd_pipe_methods xhci_device_intr_methods = {
  	.done = xhci_device_intr_done,
  };

 -static inline uint32_t
 +inline uint32_t
 +xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset)
 +{
 +	return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
 +}
 +
 +inline uint32_t
  xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset)
  {
  	return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset);
  }

 +inline void
 +xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset,
 +    uint32_t value)
 +{
 +	bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value);
 +}
 +
  #if 0 /* unused */
  static inline void
  xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset,
 @@ -899,9 +912,13 @@ xhci_intr1(struct xhci_softc * const sc)

  	iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
  	//device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman);
 -	if ((iman & XHCI_IMAN_INTR_PEND) == 0) {
 -		return 0;
 +
 +	if (!(sc->sc_xhci_quirks & XHCI_QUIRK_FORCE_INTR)) {
 +		if ((iman & XHCI_IMAN_INTR_PEND) == 0) {
 +			return 0;
 +		}
  	}
 +
  	xhci_rt_write_4(sc, XHCI_IMAN(0), iman);
  	iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
  	//device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman);
 diff --git a/usb/xhcireg.h b/usb/xhcireg.h
 index 480b93f..af9f224 100644
 --- a/usb/xhcireg.h
 +++ b/usb/xhcireg.h
 @@ -38,6 +38,11 @@
  #define	 PCI_USBREV_3_0		0x30	/* USB 3.0 */
  #define	PCI_XHCI_FLADJ		0x61	/* RW frame length adjust */

 +#define	PCI_XHCI_INTEL_XUSB2PR	0xD0    /* Intel USB2 Port Routing */
 +#define	PCI_XHCI_INTEL_USB2PRM	0xD4    /* Intel USB2 Port Routing Mask */
 +#define	PCI_XHCI_INTEL_USB3_PSSEN 0xD8  /* Intel USB3 Port SuperSpeed Enable */
 +#define	PCI_XHCI_INTEL_USB3PRM	0xDC    /* Intel USB3 Port Routing Mask */
 +
  /* XHCI capability registers */
  #define XHCI_CAPLENGTH		0x00	/* RO capability */
  #define	XHCI_CAP_CAPLENGTH(x)	((x) & 0xFF)
 @@ -188,10 +193,8 @@
  /* XHCI legacy support */
  #define	XHCI_XECP_ID(x)		((x) & 0xFF)
  #define	XHCI_XECP_NEXT(x)	(((x) >> 8) & 0xFF)
 -#if 0
  #define	XHCI_XECP_BIOS_SEM	0x0002
  #define	XHCI_XECP_OS_SEM	0x0003
 -#endif

  /* XHCI capability ID's */
  #define	XHCI_ID_USB_LEGACY	0x0001
 diff --git a/usb/xhcivar.h b/usb/xhcivar.h
 index 7ddbaa2..8b5169f 100644
 --- a/usb/xhcivar.h
 +++ b/usb/xhcivar.h
 @@ -114,8 +114,14 @@ struct xhci_softc {

  	uint8_t sc_addr;
  	uint8_t sc_conf;
 +
 +	int sc_xhci_quirks;
 +#define XHCI_QUIRK_FORCE_INTR __BIT(0) /* force interrupt reading */
  };

 +uint32_t xhci_read_1(const struct xhci_softc * const, bus_size_t);
 +uint32_t xhci_read_4(const struct xhci_softc * const, bus_size_t);
 +void	xhci_write_1(const struct xhci_softc * const, bus_size_t, uint32_t);
  int	xhci_init(struct xhci_softc *);
  int	xhci_intr(void *);
  int	xhci_detach(struct xhci_softc *, int);

 --
 Ryo ONODERA // ryo_on@yk.rim.or.jp
 PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3

From: Takahiro HAYASHI <t.hash425@gmail.com>
To: gnats-bugs@NetBSD.org, kern-bug-people@netbsd.org, ryoon@NetBSD.org
Cc: 
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Thu, 04 Sep 2014 08:59:58 +0900

 On 08/31/14 20:40, Ryo ONODERA wrote:
 [snip]
 >   +static void
 >   +xhci_pci_takecontroller(struct xhci_pci_softc *psc, int silent)
 >   +{
 >   +	uint32_t cparams, xecp, eec;
 >   +	uint8_t bios_sem;
 >   +	int i;
 >   +
 >   +	cparams = xhci_read_4(&psc->sc_xhci, XHCI_HCCPARAMS);
 >   +	eec = -1;
 >   +
 >   +	/* Synchronise with the BIOS if it owns the controller. */
 >   +	for (xecp = XHCI_HCC_XECP(cparams) << 2; xecp != 0;
 >   +	    xecp = XHCI_XECP_NEXT(eec) << 2) {
 >   +		eec = xhci_read_4(&psc->sc_xhci, xecp);

 This may not advance xecp correctly.
 According to xHCI spec 1.1 section 7, XHCI_XECP_NEXT(eec)
 indicates a relative offset in dword, "from this dword
 to the beginning of the next extended capability".
 That is, it should be:

 xecp += XHCI_XECP_NEXT(eec) << 2;

 unless XHCI_XECP_NEXT(eec) == 0.
 Please see around ID_PROTOCOL in xhci_init() for detail.


 -- 
 t-hash

From: Ryo ONODERA <ryo_on@yk.rim.or.jp>
To: t.hash425@gmail.com
Cc: gnats-bugs@NetBSD.org
Subject: Re: kern/49076: USB 3.0 devices are not attached to xhci hubs
Date: Fri, 05 Sep 2014 21:29:13 +0900 (JST)

 From: Takahiro HAYASHI <t.hash425@gmail.com>, Date: Thu, 04 Sep 2014 08:59:58 +0900

 > On 08/31/14 20:40, Ryo ONODERA wrote:
 > [snip]
 >>   +static void
 >>   +xhci_pci_takecontroller(struct xhci_pci_softc *psc, int silent)
 >>   +{
 >>   +	uint32_t cparams, xecp, eec;
 >>   +	uint8_t bios_sem;
 >>   +	int i;
 >>   +
 >>   +	cparams = xhci_read_4(&psc->sc_xhci, XHCI_HCCPARAMS);
 >>   +	eec = -1;
 >>   +
 >>   +	/* Synchronise with the BIOS if it owns the controller. */
 >>   +	for (xecp = XHCI_HCC_XECP(cparams) << 2; xecp != 0;
 >>   +	    xecp = XHCI_XECP_NEXT(eec) << 2) {
 >>   +		eec = xhci_read_4(&psc->sc_xhci, xecp);
 > 
 > This may not advance xecp correctly.
 > According to xHCI spec 1.1 section 7, XHCI_XECP_NEXT(eec)
 > indicates a relative offset in dword, "from this dword
 > to the beginning of the next extended capability".
 > That is, it should be:
 > 
 > xecp += XHCI_XECP_NEXT(eec) << 2;
 > 
 > unless XHCI_XECP_NEXT(eec) == 0.
 > Please see around ID_PROTOCOL in xhci_init() for detail.

 Hi,

 Your suggestion is correct.
 And correct XHCI_XECP_NEXT handling causes freeze during boot.
 And Intel Lynx Point does not require xhci_pci_takecontroller function.
 It was my misunderstanding.

 I withdraw xhci_pci_takecontroller part.

 Thank you.

 --
 Ryo ONODERA // ryo_on@yk.rim.or.jp
 PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3

Responsible-Changed-From-To: kern-bug-people->skrll
Responsible-Changed-By: skrll@NetBSD.org
Responsible-Changed-When: Sat, 23 Apr 2016 19:08:58 +0000
Responsible-Changed-Why:
Take


State-Changed-From-To: open->feedback
State-Changed-By: skrll@NetBSD.org
State-Changed-When: Sat, 23 Apr 2016 19:08:58 +0000
State-Changed-Why:
OK to close with nick-nhusb merge?


From: Ryo ONODERA <ryo_on@yk.rim.or.jp>
To: gnats-bugs@NetBSD.org, skrll@NetBSD.org
Cc: 
Subject: Re: kern/49076 (USB 3.0 devices are not attached to xhci hubs)
Date: Sat, 30 Apr 2016 17:05:28 +0900 (JST)

 From: skrll@NetBSD.org, Date: Sat, 23 Apr 2016 19:08:58 +0000 (UTC)

 > Synopsis: USB 3.0 devices are not attached to xhci hubs

 > State-Changed-From-To: open->feedback
 > State-Changed-By: skrll@NetBSD.org
 > State-Changed-When: Sat, 23 Apr 2016 19:08:58 +0000
 > State-Changed-Why:
 > OK to close with nick-nhusb merge?

 Non-root USB 3.0 hub (ELECOM U3H-A407B) works fine.
 Basically original problem is already fixed.

 However iBUFFALO BSH4U21U3 USB 3.0 hub cannot accept USB 3.0 device.
 I will create another PR later.

 Thanks for your great work.

 --
 Ryo ONODERA // ryo_on@yk.rim.or.jp
 PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB  FD1B F404 27FA C7D1 15F3

State-Changed-From-To: feedback->closed
State-Changed-By: skrll@NetBSD.org
State-Changed-When: Sat, 30 Apr 2016 09:58:08 +0000
State-Changed-Why:
Confirmed by submitter


>Unformatted:

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