NetBSD Problem Report #49468
From www@NetBSD.org Sat Dec 13 16:15:21 2014
Return-Path: <www@NetBSD.org>
Received: from mail.netbsd.org (mail.netbsd.org [149.20.53.66])
(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
(Client CN "mail.netbsd.org", Issuer "Postmaster NetBSD.org" (verified OK))
by mollari.NetBSD.org (Postfix) with ESMTPS id A2274A567D
for <gnats-bugs@gnats.NetBSD.org>; Sat, 13 Dec 2014 16:15:21 +0000 (UTC)
Message-Id: <20141213161520.4BED3A6553@mollari.NetBSD.org>
Date: Sat, 13 Dec 2014 16:15:20 +0000 (UTC)
From: jmcneill@invisible.ca
Reply-To: jmcneill@invisible.ca
To: gnats-bugs@NetBSD.org
Subject: Cortex GIC assertion triggered on Allwinner A80 SoC
X-Send-Pr-Version: www-1.0
>Number: 49468
>Category: port-evbarm
>Synopsis: Cortex GIC assertion triggered on Allwinner A80 SoC
>Confidential: no
>Severity: critical
>Priority: high
>Responsible: jmcneill
>State: closed
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Sat Dec 13 16:20:00 +0000 2014
>Closed-Date: Wed Feb 07 22:56:40 +0000 2018
>Last-Modified: Wed Feb 07 22:56:40 +0000 2018
>Originator: Jared McNeill
>Release: 7.99.2
>Organization:
>Environment:
NetBSD 7.99.2 (ALLWINNER_A80) #208: Sat Dec 13 12:07:36 AST 2014
>Description:
I seem to be getting random panics in gic.c on A80. Usually (but not always) happens at some point while booting. Doesn't make a difference if UP or MP.
Starting root file system check:
panic: kernel diagnostic assertion "old_ipl != IPL_HIGH" failed: file "/Users/jmcneill/branches/HEAD/src/sys/arch/arm/cortex/gic.c", line 235 old_ipl 7 pmr 0x80 hppir 0xc
Stopped in pid 0.31 (system) at netbsd:cpu_Debugger+0x4: bx r14
db{3}> bt
0xbff29e4c: netbsd:vpanic+0xc
0xbff29e64: netbsd:__udivmoddi4
0xbff29ecc: netbsd:armgic_irq_handler+0x2f0
0xbff29f3c: netbsd:irq_entry+0x60
0xbff29f64: netbsd:_splraise+0x3c
0xbff29fac: netbsd:softint_dispatch+0xec
0xbff31f54: netbsd:softint_switch+0x50
0xbff31f6c: netbsd:cpu_idle+0x48
0xbff31f94: netbsd:idle_loop+0x170
>How-To-Repeat:
Boot an ALLWINNER_A80 kernel multi-user.
>Fix:
>Release-Note:
>Audit-Trail:
From: "Jared D. McNeill" <jmcneill@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc:
Subject: PR/49468 CVS commit: src/sys/arch/arm/cortex
Date: Wed, 7 Feb 2018 20:42:17 +0000
Module Name: src
Committed By: jmcneill
Date: Wed Feb 7 20:42:17 UTC 2018
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoC
The priority level is changed by writing to GICC_PMR with interrupts
disabled. However, interrupts are enabled/disabled downstream of the GICC
at the CPU. When raising priority level, there is a window between the time
that interrupts are disabled and the GICC_PMR register is written. If an
interrupt occurs at a previously allowed priority before GICC_PMR is
changed, the CPU will receive the signal when interrupts are re-enabled.
At this time, GICC_PMR is now the new priority level, so reads of
GICC_IAR will report a spurious IRQ.
Move the "old_ipl != IPL_HIGH" test until after we have confirmed that
there is at least one pending IRQ.
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Responsible-Changed-From-To: port-evbarm-maintainer->jmcneill
Responsible-Changed-By: jmcneill@NetBSD.org
Responsible-Changed-When: Wed, 07 Feb 2018 22:56:40 +0000
Responsible-Changed-Why:
take
State-Changed-From-To: open->closed
State-Changed-By: jmcneill@NetBSD.org
State-Changed-When: Wed, 07 Feb 2018 22:56:40 +0000
State-Changed-Why:
Fixed: http://mail-index.netbsd.org/source-changes/2018/02/07/msg091917.html
>Unformatted:
(Contact us)
$NetBSD: query-full-pr,v 1.43 2018/01/16 07:36:43 maya Exp $
$NetBSD: gnats_config.sh,v 1.9 2014/08/02 14:16:04 spz Exp $
Copyright © 1994-2017
The NetBSD Foundation, Inc. ALL RIGHTS RESERVED.