NetBSD Problem Report #52119

From www@NetBSD.org  Tue Mar 28 03:29:12 2017
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	for <gnats-bugs@gnats.NetBSD.org>; Tue, 28 Mar 2017 03:29:12 +0000 (UTC)
Message-Id: <20170328032911.7C6E67A26D@mollari.NetBSD.org>
Date: Tue, 28 Mar 2017 03:29:11 +0000 (UTC)
From: n54@gmx.com
Reply-To: n54@gmx.com
To: gnats-bugs@NetBSD.org
Subject: PT_STEP not supported on arm 32-bit
X-Send-Pr-Version: www-1.0

>Number:         52119
>Notify-List:    bsiegert@NetBSD.org
>Category:       port-arm
>Synopsis:       PT_STEP not supported on arm 32-bit
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    port-arm-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Tue Mar 28 03:30:00 +0000 2017
>Closed-Date:    
>Last-Modified:  Mon Aug 20 18:20:11 +0000 2018
>Originator:     Kamil Rytarowski
>Release:        NetBSD 7.99.66 amd64
>Organization:
TNF
>Environment:
NetBSD chieftec 7.99.66 NetBSD 7.99.66 (GENERIC) #3: Tue Mar 28 02:01:26 CEST 2017  root@chieftec:/public/netbsd-root/sys/arch/amd64/compile/GENERIC amd64
>Description:
ptrace(2) PT_STEP is not supported on arm.
>How-To-Repeat:
Try to use it or run t_ptrace_wait* tests.
>Fix:
Implement software emulated PT_STEP.

>Release-Note:

>Audit-Trail:

Responsible-Changed-From-To: port-arm-maintainer->skrll
Responsible-Changed-By: skrll@NetBSD.org
Responsible-Changed-When: Tue, 28 Mar 2017 05:37:40 +0000
Responsible-Changed-Why:
Take - I'm close to having this working


From: "Kamil Rytarowski" <kamil@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/52119 CVS commit: src/tests/kernel
Date: Tue, 28 Mar 2017 12:39:07 +0000

 Module Name:	src
 Committed By:	kamil
 Date:		Tue Mar 28 12:39:07 UTC 2017

 Modified Files:
 	src/tests/kernel: t_ptrace_wait.c

 Log Message:
 Mark PT_STEP tests in t_ptrace_wait* as broken on ARM

 There is a definition of PT_STEP for userland, but no implementation
 in the kernel.

 PR kern/52119 PT_STEP not supported on arm 32-bit

 Sponsored by <The NetBSD Foundation>


 To generate a diff of this commit:
 cvs rdiff -u -r1.82 -r1.83 src/tests/kernel/t_ptrace_wait.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

Responsible-Changed-From-To: skrll->port-arm-maintainer
Responsible-Changed-By: skrll@NetBSD.org
Responsible-Changed-When: Fri, 14 Apr 2017 11:14:44 +0000
Responsible-Changed-Why:
punt


From: Nick Hudson <skrll@netbsd.org>
To: gnats-bugs@NetBSD.org, port-arm-maintainer@netbsd.org,
 gnats-admin@netbsd.org, netbsd-bugs@netbsd.org
Cc: 
Subject: Re: port-arm/52119: PT_STEP not supported on arm 32-bit
Date: Fri, 14 Apr 2017 10:44:21 +0100

 This is a multi-part message in MIME format.
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 This is as far as I got... lots borrowed from FreeBSD.

 --------------080500010605080702030803
 Content-Type: text/x-patch;
  name="arm.pt_step.diff"
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  filename="arm.pt_step.diff"

 Index: sys/arch/arm/arm/arm_machdep.c
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/arm/arm_machdep.c,v
 retrieving revision 1.51
 diff -u -p -r1.51 arm_machdep.c
 --- sys/arch/arm/arm/arm_machdep.c	4 Apr 2017 11:46:12 -0000	1.51
 +++ sys/arch/arm/arm/arm_machdep.c	13 Apr 2017 10:20:38 -0000
 @@ -356,3 +356,116 @@ cpu_kpreempt_disabled(void)
  	return curcpu()->ci_cpl != IPL_NONE;
  }
  #endif /* __HAVE_PREEMPTION */
 +
 +int
 +arm_predict_branch(void *cookie, u_int insn, register_t pc, register_t *new_pc,
 +    u_int (*fetch_reg)(void *, int), u_int (*read_int)(void *, vaddr_t, u_int*))
 +{
 +	u_int addr, nregs, offset = 0;
 +	int error = 0;
 +
 +	switch ((insn >> 24) & 0xf) {
 +	case 0x2:	/* add pc, reg1, #value */
 +	case 0x0:	/* add pc, reg1, reg2, lsl #offset */
 +
 +		/* Data-processin and miscellaneous A5-196 */
 +		addr = fetch_reg(cookie, (insn >> 16) & 0xf);
 +		if (((insn >> 16) & 0xf) == 15)
 +			addr += 8;
 +		if (insn & 0x0200000) {
 +			offset = (insn >> 7) & 0x1e;
 +			offset = (insn & 0xff) << (32 - offset) |
 +			    (insn & 0xff) >> offset;
 +		} else {
 +
 +			offset = fetch_reg(cookie, insn & 0x0f);
 +			if ((insn & 0x0000ff0) != 0x00000000) {
 +				if (insn & 0x10)
 +					nregs = fetch_reg(cookie,
 +					    (insn >> 8) & 0xf);
 +				else
 +					nregs = (insn >> 7) & 0x1f;
 +				switch ((insn >> 5) & 3) {
 +				case 0:
 +					/* lsl */
 +					offset = offset << nregs;
 +					break;
 +				case 1:
 +					/* lsr */
 +					offset = offset >> nregs;
 +					break;
 +				default:
 +					break; /* XXX */
 +				}
 +
 +			}
 +			*new_pc = addr + offset;
 +			return 0;
 +
 +		}
 +
 +	case 0xa:	/* b ... */
 +	case 0xb:	/* bl ... */
 +		addr = ((insn << 2) & 0x03ffffff);
 +		if (addr & 0x02000000)
 +			addr |= 0xfc000000;
 +		*new_pc = (pc + 8 + addr);
 +		return 0;
 +	case 0x7:	/* ldr pc, [pc, reg, lsl #2] */
 +
 +		/* Load/store A5-208 */
 +		/* XXX op1 = 0x11, op (bit 4) = 0 */
 +
 +		addr = fetch_reg(cookie, insn & 0xf);
 +		addr = pc + 8 + (addr << 2);
 +		error = read_int(cookie, addr, &addr);
 +		*new_pc = addr;
 +		return error;
 +	case 0x1:	/* mov pc, reg */
 +    		/* Data-processing and miscellaneous A5-196 */
 +
 +		*new_pc = fetch_reg(cookie, insn & 0xf);
 +		return 0;
 +	case 0x4:
 +	case 0x5:	/* ldr pc, [reg] */
 +		addr = fetch_reg(cookie, (insn >> 16) & 0xf);
 +		/* ldr pc, [reg, #offset] */
 +		if (insn & (1 << 24))
 +			offset = insn & 0xfff;
 +		if (insn & 0x00800000)
 +			addr += offset;
 +		else
 +			addr -= offset;
 +		error = read_int(cookie, addr, &addr);
 +		*new_pc = addr;
 +
 +		return error;
 +	case 0x8:	/* ldmxx reg, {..., pc} */
 +	case 0x9:
 +		addr = fetch_reg(cookie, (insn >> 16) & 0xf);
 +		nregs = (insn  & 0x5555) + ((insn  >> 1) & 0x5555);
 +		nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333);
 +		nregs = (nregs + (nregs >> 4)) & 0x0f0f;
 +		nregs = (nregs + (nregs >> 8)) & 0x001f;
 +		switch ((insn >> 23) & 0x3) {
 +		case 0x0:	/* ldmda */
 +			addr = addr - 0;
 +			break;
 +		case 0x1:	/* ldmia */
 +			addr = addr + 0 + ((nregs - 1) << 2);
 +			break;
 +		case 0x2:	/* ldmdb */
 +			addr = addr - 4;
 +			break;
 +		case 0x3:	/* ldmib */
 +			addr = addr + 4 + ((nregs - 1) << 2);
 +			break;
 +		}
 +		error = read_int(cookie, addr, &addr);
 +		*new_pc = addr;
 +
 +		return error;
 +	default:
 +		return EINVAL;
 +	}
 +}
 Index: sys/arch/arm/arm/process_machdep.c
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/arm/process_machdep.c,v
 retrieving revision 1.32
 diff -u -p -r1.32 process_machdep.c
 --- sys/arch/arm/arm/process_machdep.c	16 Mar 2017 16:13:20 -0000	1.32
 +++ sys/arch/arm/arm/process_machdep.c	13 Apr 2017 10:20:38 -0000
 @@ -143,6 +143,7 @@ __KERNEL_RCSID(0, "$NetBSD: process_mach
  #include <arm/vfpreg.h>
  #include <arm/locore.h>

 +#include <machine/db_machdep.h>
  #include <machine/pcb.h>
  #include <machine/reg.h>

 @@ -250,3 +251,171 @@ process_set_pc(struct lwp *l, void *addr

  	return 0;
  }
 +
 +static int
 +ptrace_read_int(struct lwp *l, vaddr_t addr, uint32_t *v)
 +{
 +
 +	return proc_readmem(curlwp, l, addr, v, sizeof(*v));
 +}
 +
 +static int
 +ptrace_write_int(struct lwp *l, vaddr_t addr, uint32_t v)
 +{
 +
 +	return proc_writemem(curlwp, l, addr, &v, sizeof(v));
 +}
 +
 +static u_int
 +ptrace_get_usr_reg(void *cookie, int reg)
 +{
 +	struct lwp * const l = cookie;
 +	struct trapframe * const tf = lwp_trapframe(l);
 +	int ret;
 +
 +	KASSERTMSG(reg >= 0 && reg <= ARM_REG_NUM_PC,
 +	    "reg (%d) is outside range", reg);
 +
 +	switch(reg) {
 +	case ARM_REG_NUM_PC:
 +		ret = tf->tf_pc;
 +		break;
 +	case ARM_REG_NUM_LR:
 +		ret = tf->tf_usr_lr;
 +		break;
 +	case ARM_REG_NUM_SP:
 +		ret = tf->tf_usr_sp;
 +		break;
 +	default:
 +		ret = *((register_t*)&tf->tf_r0 + reg);
 +		break;
 +	}
 +
 +	return ret;
 +}
 +
 +static u_int
 +ptrace_get_usr_int(void *cookie, vaddr_t offset, u_int *val)
 +{
 +	struct lwp * const l = cookie;
 +
 +	return ptrace_read_int(l, offset, val);
 +}
 +
 +/**
 + * This function parses current instruction opcode and decodes
 + * any possible jump (change in PC) which might occur after
 + * the instruction is executed.
 + *
 + * @param     l                 LWP structure of analysed thread
 + * @param     cur_instr         Currently executed instruction
 + * @param     alt_next_address  Pointer to the variable where
 + *                              the destination address of the
 + *                              jump instruction shall be stored.
 + *
 + * @return    <0>               when jump is possible
 + *            <EINVAL>          otherwise
 + */
 +static int
 +ptrace_get_alternative_next(struct lwp *l, uint32_t cur_instr,
 +    uint32_t *alt_next_address)
 +{
 +	int error;
 +
 +	if (inst_branch(cur_instr) || inst_call(cur_instr) ||
 +	    inst_return(cur_instr)) {
 +		struct trapframe * const tf = lwp_trapframe(l);
 +		error = arm_predict_branch(l, cur_instr, tf->tf_pc,
 +		    alt_next_address, ptrace_get_usr_reg, ptrace_get_usr_int);
 +
 +		return error;
 +	}
 +
 +	return EINVAL;
 +}
 +
 +int
 +process_sstep(struct lwp *l, int sstep)
 +{
 +	struct trapframe * const tf = lwp_trapframe(l);
 +	uint32_t cur_instr, alt_next = 0;
 +
 +	/* TODO: This needs to be updated for Thumb-2 */
 +	if ((tf->tf_spsr & PSR_T_bit) != 0)
 +		return EINVAL;
 +
 +	process_clear_sstep(l);
 +
 +	/* We're continuing... */
 +	if (sstep == 0) {
 +		return 0;
 +	}
 +
 +	KASSERTMSG(l->l_md.md_ptrace_instr == 0, "Didn't clear single step");
 +	KASSERTMSG(l->l_md.md_ptrace_instr_alt == 0,
 +	    "Didn't clear alternative single step");
 +
 +	int error;
 +	error = ptrace_read_int(l, tf->tf_pc, &cur_instr);
 +	if (error)
 +		return error;
 +
 +	error = ptrace_read_int(l, tf->tf_pc + INSN_SIZE,
 +	    &l->l_md.md_ptrace_instr);
 +	if (error)
 +		return error;
 +
 +	error = ptrace_write_int(l, tf->tf_pc + INSN_SIZE,
 +	    PTRACE_BREAKPOINT_INSN);
 +	if (error) {
 +		l->l_md.md_ptrace_instr = 0;
 +		return error;
 +	}
 +
 +	l->l_md.md_ptrace_addr = tf->tf_pc + INSN_SIZE;
 +	error = ptrace_get_alternative_next(l, cur_instr, &alt_next);
 +	if (error)
 +		return 0;
 +
 +	error = ptrace_read_int(l, alt_next, &l->l_md.md_ptrace_instr_alt);
 +	if (error) {
 +		l->l_md.md_ptrace_instr_alt = 0;
 +		return error;
 +	}
 +
 +	error = ptrace_write_int(l, alt_next, PTRACE_BREAKPOINT_INSN);
 +	if (error) {
 +		l->l_md.md_ptrace_instr_alt = 0;
 +		return error;
 +	}
 +
 +	l->l_md.md_ptrace_addr_alt = alt_next;
 +
 +	return 0;
 +}
 +
 +int
 +process_clear_sstep(struct lwp *l)
 +{
 +	struct trapframe * const tf = lwp_trapframe(l);
 +
 +	/* TODO: This needs to be updated for Thumb-2 */
 +	if ((tf->tf_spsr & PSR_T_bit) != 0)
 +		return EINVAL;
 +
 +	if (l->l_md.md_ptrace_instr != 0) {
 +		ptrace_write_int(l, l->l_md.md_ptrace_addr,
 +		    l->l_md.md_ptrace_instr);
 +		l->l_md.md_ptrace_instr = 0;
 +	}
 +	l->l_md.md_ptrace_addr = 0;
 +
 +	if (l->l_md.md_ptrace_instr_alt != 0) {
 +		ptrace_write_int(l, l->l_md.md_ptrace_addr_alt,
 +		    l->l_md.md_ptrace_instr_alt);
 +		l->l_md.md_ptrace_instr_alt = 0;
 +	}
 +	l->l_md.md_ptrace_addr_alt = 0;
 +
 +	return 0;
 +}
 Index: sys/arch/arm/arm/undefined.c
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/arm/undefined.c,v
 retrieving revision 1.58
 diff -u -p -r1.58 undefined.c
 --- sys/arch/arm/arm/undefined.c	27 Feb 2017 06:46:59 -0000	1.58
 +++ sys/arch/arm/arm/undefined.c	13 Apr 2017 10:20:38 -0000
 @@ -47,8 +47,9 @@
  #define FAST_FPE

  #include "opt_ddb.h"
 -#include "opt_kgdb.h"
  #include "opt_dtrace.h"
 +#include "opt_kgdb.h"
 +#include "opt_ptrace.h"

  #include <sys/param.h>
  #ifdef KGDB
 @@ -85,11 +86,18 @@ __KERNEL_RCSID(0, "$NetBSD: undefined.c,
  #include <machine/db_machdep.h>
  #endif

 +#ifdef PTRACE
 +#include <sys/ptrace.h>
 +#endif
 +
  #ifdef acorn26
  #include <machine/machdep.h>
  #endif

  static int gdb_trapper(u_int, u_int, struct trapframe *, int);
 +#ifdef PTRACE
 +static int ptrace_trapper(u_int, u_int, struct trapframe *, int);
 +#endif

  LIST_HEAD(, undefined_handler) undefined_handlers[NUM_UNKNOWN_HANDLERS];

 @@ -212,6 +220,38 @@ gdb_trapper(u_int addr, u_int insn, stru
  	return 1;
  }

 +#ifdef PTRACE
 +static struct undefined_handler ptrace_uh;
 +
 +static int
 +ptrace_trapper(u_int addr, u_int insn, struct trapframe *tf, int code)
 +{
 +	/* TODO: No support for ptrace from Thumb-2 */
 +	if ((tf->tf_spsr & PSR_T_bit))
 +		return 1;
 +
 +	if (insn == PTRACE_BREAKPOINT_INSN) {
 +		struct lwp * const l = curlwp;
 +		const bool sstep =
 +		   addr == l->l_md.md_ptrace_addr ||
 +		   addr == l->l_md.md_ptrace_addr_alt;
 +
 +		process_clear_sstep(l);
 +		ksiginfo_t ksi;
 +		KSI_INIT_TRAP(&ksi);
 +		ksi.ksi_signo = SIGTRAP;
 +		ksi.ksi_code = sstep ? TRAP_TRACE : TRAP_BRKPT;
 +		ksi.ksi_addr = (uint32_t *)addr;
 +		ksi.ksi_trap = insn;
 +		trapsignal(l, &ksi);
 +		return 0;
 +	}
 +
 +	return 1;
 +}
 +#endif
 +
 +
  static struct undefined_handler cp15_uh;
  static struct undefined_handler gdb_uh;
  #ifdef THUMB_CODE
 @@ -273,6 +313,12 @@ undefined_init(void)
  	/* Install handler for GDB breakpoints */
  	gdb_uh.uh_handler = gdb_trapper;
  	install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &gdb_uh);
 +
 +#ifdef PTRACE
 +	/* Install handler for PTRACE breakpoints */
 +	ptrace_uh.uh_handler = ptrace_trapper;
 +	install_coproc_handler_static(CORE_UNKNOWN_HANDLER, &ptrace_uh);
 +#endif
  #ifdef THUMB_CODE
  	gdb_uh_thumb.uh_handler = gdb_trapper;
  	install_coproc_handler_static(THUMB_UNKNOWN_HANDLER, &gdb_uh_thumb);
 Index: sys/arch/arm/arm32/db_interface.c
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/arm32/db_interface.c,v
 retrieving revision 1.54
 diff -u -p -r1.54 db_interface.c
 --- sys/arch/arm/arm32/db_interface.c	29 Oct 2014 14:14:14 -0000	1.54
 +++ sys/arch/arm/arm32/db_interface.c	13 Apr 2017 10:20:38 -0000
 @@ -51,6 +51,7 @@ __KERNEL_RCSID(0, "$NetBSD: db_interface

  #include <uvm/uvm_extern.h>

 +#include <arm/arm32/machdep.h>
  #include <arm/arm32/db_machdep.h>
  #include <arm/undefined.h>
  #include <ddb/db_access.h>
 @@ -462,54 +463,38 @@ db_fetch_reg(int reg, db_regs_t *regs)
  	}
  }

 +static u_int
 +db_branch_taken_read_int(void *cookie __unused, vaddr_t va, u_int *val)
 +{
 +	u_int ret;
 +
 +	db_read_bytes(va, sizeof(ret), (char *)&ret);
 +	*val = ret;
 +
 +	return 0;
 +}
 +
 +static u_int
 +db_branch_taken_fetch_reg(void *cookie, int reg)
 +{
 +	db_regs_t *regs = cookie;
 +
 +	return db_fetch_reg(reg, regs);
 +}
 +
  u_int
  branch_taken(u_int insn, u_int pc, db_regs_t *regs)
  {
 -	u_int addr, nregs;
 +	register_t new_pc;
 +	int ret;

 -	switch ((insn >> 24) & 0xf) {
 -	case 0xa:	/* b ... */
 -	case 0xb:	/* bl ... */
 -		addr = ((insn << 2) & 0x03ffffff);
 -		if (addr & 0x02000000)
 -			addr |= 0xfc000000;
 -		return (pc + 8 + addr);
 -	case 0x7:	/* ldr pc, [pc, reg, lsl #2] */
 -		addr = db_fetch_reg(insn & 0xf, regs);
 -		addr = pc + 8 + (addr << 2);
 -		db_read_bytes(addr, 4, (char *)&addr);
 -		return (addr);
 -	case 0x5:	/* ldr pc, [reg] */
 -		addr = db_fetch_reg((insn >> 16) & 0xf, regs);
 -		db_read_bytes(addr, 4, (char *)&addr);
 -		return (addr);
 -	case 0x1:	/* mov pc, reg */
 -		addr = db_fetch_reg(insn & 0xf, regs);
 -		return (addr);
 -	case 0x8:	/* ldmxx reg, {..., pc} */
 -	case 0x9:
 -		addr = db_fetch_reg((insn >> 16) & 0xf, regs);
 -		nregs = (insn  & 0x5555) + ((insn  >> 1) & 0x5555);
 -		nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333);
 -		nregs = (nregs + (nregs >> 4)) & 0x0f0f;
 -		nregs = (nregs + (nregs >> 8)) & 0x001f;
 -		switch ((insn >> 23) & 0x3) {
 -		case 0x0:	/* ldmda */
 -			addr = addr - 0;
 -			break;
 -		case 0x1:	/* ldmia */
 -			addr = addr + 0 + ((nregs - 1) << 2);
 -			break;
 -		case 0x2:	/* ldmdb */
 -			addr = addr - 4;
 -			break;
 -		case 0x3:	/* ldmib */
 -			addr = addr + 4 + ((nregs - 1) << 2);
 -			break;
 -		}
 -		db_read_bytes(addr, 4, (char *)&addr);
 -		return (addr);
 -	default:
 -		panic("branch_taken: botch");
 +	ret = arm_predict_branch(regs, insn, pc, &new_pc,
 +	    db_branch_taken_fetch_reg, db_branch_taken_read_int);
 +
 +	if (ret != 0) {
 +		panic("what now");
 +		//kdb_reenter();
  	}
 +
 +	return new_pc;
  }
 Index: sys/arch/arm/include/armreg.h
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/include/armreg.h,v
 retrieving revision 1.111
 diff -u -p -r1.111 armreg.h
 --- sys/arch/arm/include/armreg.h	17 May 2016 08:27:24 -0000	1.111
 +++ sys/arch/arm/include/armreg.h	13 Apr 2017 10:20:39 -0000
 @@ -604,6 +604,12 @@

  #define THUMB_INSN_SIZE		2		/* Some are 4 bytes.  */

 +/* ARM register defines */
 +#define	ARM_REG_SIZE		4
 +#define	ARM_REG_NUM_PC		15
 +#define	ARM_REG_NUM_LR		14
 +#define	ARM_REG_NUM_SP		13
 +
  /*
   * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0)
   */
 Index: sys/arch/arm/include/cpu.h
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/include/cpu.h,v
 retrieving revision 1.93
 diff -u -p -r1.93 cpu.h
 --- sys/arch/arm/include/cpu.h	4 Apr 2017 09:26:32 -0000	1.93
 +++ sys/arch/arm/include/cpu.h	13 Apr 2017 10:20:39 -0000
 @@ -315,6 +315,9 @@ void	cpu_set_curpri(int);
   */
  vaddr_t cpu_uarea_alloc_idlelwp(struct cpu_info *);

 +int arm_predict_branch(void *, u_int, register_t, register_t *,
 +    u_int (*)(void *, int), u_int (*)(void *, vaddr_t, u_int *));
 +
  #ifndef acorn26
  /*
   * cpu device glue (belongs in cpuvar.h)
 Index: sys/arch/arm/include/db_machdep.h
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/include/db_machdep.h,v
 retrieving revision 1.24
 diff -u -p -r1.24 db_machdep.h
 --- sys/arch/arm/include/db_machdep.h	20 Feb 2017 17:27:32 -0000	1.24
 +++ sys/arch/arm/include/db_machdep.h	13 Apr 2017 10:20:39 -0000
 @@ -91,7 +91,8 @@ extern db_regs_t *ddb_regp;
  /* mov pc, reg
  					    0000000f  register */
  #define	inst_return(ins)	(((ins) & 0x0e108000) == 0x08108000 || \
 -				 ((ins) & 0x0ff0fff0) == 0x01a0f000)
 +				 ((ins) & 0x0ff0fff0) == 0x01a0f000 ||	\
 +				 ((ins) & 0x0ffffff0) == 0x012fff10) /* bx */
  /* bl ...
  					    00ffffff  offset>>2 */
  #define	inst_call(ins)		(((ins) & 0x0f000000) == 0x0b000000)
 @@ -99,9 +100,13 @@ extern db_regs_t *ddb_regp;
  					    00ffffff  offset>>2 */
  /* ldr pc, [pc, reg, lsl #2]
  					    0000000f  register */
 +
  #define	inst_branch(ins)	(((ins) & 0x0f000000) == 0x0a000000 || \
  				 ((ins) & 0x0fdffff0) == 0x079ff100 || \
 -				 ((ins) & 0x0ff0f000) == 0x0590f000)
 +				 ((ins) & 0x0cd0f000) == 0x0490f000 || \
 +				 ((ins) & 0x0ffffff0) == 0x012fff30 || /* blx */ \
 +				 ((ins) & 0x0de0f000) == 0x0080f000)
 +
  #define inst_load(ins)		(0)
  #define inst_store(ins)		(0)
  #define inst_unconditional_flow_transfer(ins)	\
 Index: sys/arch/arm/include/proc.h
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/include/proc.h,v
 retrieving revision 1.17
 diff -u -p -r1.17 proc.h
 --- sys/arch/arm/include/proc.h	24 Feb 2014 16:57:57 -0000	1.17
 +++ sys/arch/arm/include/proc.h	13 Apr 2017 10:20:39 -0000
 @@ -44,7 +44,11 @@ struct lwp;

  struct mdlwp {
  	struct trapframe *md_tf;
 -	int	md_flags;
 +	int md_flags;
 +	int md_ptrace_instr;
 +	int md_ptrace_addr;
 +	int md_ptrace_instr_alt;
 +	int md_ptrace_addr_alt;
  };

  /* Flags setttings for md_flags */
 Index: sys/arch/arm/include/ptrace.h
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/arm/include/ptrace.h,v
 retrieving revision 1.11
 diff -u -p -r1.11 ptrace.h
 --- sys/arch/arm/include/ptrace.h	12 Apr 2017 18:17:59 -0000	1.11
 +++ sys/arch/arm/include/ptrace.h	13 Apr 2017 10:20:39 -0000
 @@ -34,18 +34,14 @@
  /*
   * arm-dependent ptrace definitions
   */
 -#ifndef _KERNEL
 -#define PT_STEP		(PT_FIRSTMACH + 0) /* Not implemented */
 -#endif
 +#define	PT_STEP		(PT_FIRSTMACH + 0)
  #define	PT_GETREGS	(PT_FIRSTMACH + 1)
  #define	PT_SETREGS	(PT_FIRSTMACH + 2)
  /* 3 and 4 are for FPE registers */
  #define	PT_GETFPREGS	(PT_FIRSTMACH + 5)
  #define	PT_SETFPREGS	(PT_FIRSTMACH + 6)
 -#ifndef _KERNEL
 -#define PT_SETSTEP	(PT_FIRSTMACH + 7) /* Not implemented */
 -#define PT_CLEARSTEP	(PT_FIRSTMACH + 8) /* Not implemented */
 -#endif
 +#define PT_SETSTEP	(PT_FIRSTMACH + 7)
 +#define PT_CLEARSTEP	(PT_FIRSTMACH + 8)

  #define PT_MACHDEP_STRINGS \
  	"PT_STEP", \
 @@ -68,3 +64,7 @@
  #define PTRACE_BREAKPOINT_INSN	0xe7fffffe
  #define PTRACE_BREAKPOINT_ASM	__asm __volatile (".word " ___STRING(PTRACE_BREAKPOINT_INSN) )
  #define PTRACE_BREAKPOINT_SIZE	4
 +
 +struct lwp;
 +int	process_clear_sstep(struct lwp *);
 +
 Index: sys/arch/hppa/include/ptrace.h
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/hppa/include/ptrace.h,v
 retrieving revision 1.8
 diff -u -p -r1.8 ptrace.h
 --- sys/arch/hppa/include/ptrace.h	12 Apr 2017 18:17:59 -0000	1.8
 +++ sys/arch/hppa/include/ptrace.h	13 Apr 2017 10:20:42 -0000
 @@ -60,3 +60,7 @@
  #define PTRACE_BREAKPOINT	((const uint8_t[]) { 0x00, 0x01, 0x00, 0x04 })
  #define PTRACE_BREAKPOINT_ASM	__asm __volatile("break	%0, %1" :: "i" (HPPA_BREAK_KERNEL), "i" (HPPA_BREAK_SS) : "memory")
  #define PTRACE_BREAKPOINT_SIZE	4
 +
 +struct lwp;
 +int     process_clear_sstep(struct lwp *);
 +
 Index: sys/kern/sys_process.c
 ===================================================================
 RCS file: /cvsroot/src/sys/kern/sys_process.c,v
 retrieving revision 1.179
 diff -u -p -r1.179 sys_process.c
 --- sys/kern/sys_process.c	13 Apr 2017 07:58:45 -0000	1.179
 +++ sys/kern/sys_process.c	13 Apr 2017 10:20:39 -0000
 @@ -145,6 +145,42 @@ __KERNEL_RCSID(0, "$NetBSD: sys_process.
  #include <machine/reg.h>

  #if defined(KTRACE) || defined(PTRACE_HOOKS)
 +
 +static int
 +proc_iop(struct lwp *curl, struct lwp *l, vaddr_t va, void *buf,
 +    size_t len, enum uio_rw rw)
 +{
 +	struct uio uio;
 +	struct iovec iov;
 +
 +	iov.iov_base = buf;
 +	iov.iov_len = len;
 +	uio.uio_iov = &iov;
 +	uio.uio_iovcnt = 1;
 +	uio.uio_offset = va;
 +	uio.uio_resid = len;
 +	uio.uio_rw = rw;
 +	UIO_SETUP_SYSSPACE(&uio);
 +
 +	return process_domem(curl, l, &uio);
 +}
 +
 +int
 +proc_readmem(struct lwp *curl, struct lwp *l, vaddr_t va, void *buf,
 +    size_t len)
 +{
 +
 +	return proc_iop(curl, l, va, buf, len, UIO_READ);
 +}
 +
 +int
 +proc_writemem(struct lwp *curl, struct lwp *l, vaddr_t va, void *buf,
 +    size_t len)
 +{
 +
 +	return proc_iop(curl, l, va, buf, len, UIO_WRITE);
 +}
 +
  int
  process_domem(struct lwp *curl /*tracer*/,
      struct lwp *l /*traced*/,
 Index: sys/sys/ptrace.h
 ===================================================================
 RCS file: /cvsroot/src/sys/sys/ptrace.h,v
 retrieving revision 1.60
 diff -u -p -r1.60 ptrace.h
 --- sys/sys/ptrace.h	24 Mar 2017 17:40:44 -0000	1.60
 +++ sys/sys/ptrace.h	13 Apr 2017 10:20:39 -0000
 @@ -212,6 +212,8 @@ void	proc_stoptrace(int);
  void	proc_reparent(struct proc *, struct proc *);
  void	proc_changeparent(struct proc *, struct proc *);

 +int	proc_readmem(struct lwp *, struct lwp *, vaddr_t, void *, size_t);
 +int	proc_writemem(struct lwp *, struct lwp *, vaddr_t, void *, size_t);

  int	do_ptrace(struct ptrace_methods *, struct lwp *, int, pid_t, void *,
  	    int, register_t *);
 Index: sys/arch/hppa/hppa/trap.c
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/hppa/hppa/trap.c,v
 retrieving revision 1.107
 diff -u -p -r1.107 trap.c
 --- sys/arch/hppa/hppa/trap.c	2 Mar 2015 11:05:12 -0000	1.107
 +++ sys/arch/hppa/hppa/trap.c	13 Apr 2017 10:20:41 -0000
 @@ -1015,40 +1015,16 @@ cpu_spawn_return(struct lwp *l)

  #include <sys/ptrace.h>

 -int
 +static inline int
  ss_get_value(struct lwp *l, vaddr_t addr, u_int *value)
  {
 -	struct uio uio;
 -	struct iovec iov;
 -
 -	iov.iov_base = (void *)value;
 -	iov.iov_len = sizeof(u_int);
 -	uio.uio_iov = &iov;
 -	uio.uio_iovcnt = 1;
 -	uio.uio_offset = (off_t)addr;
 -	uio.uio_resid = sizeof(u_int);
 -	uio.uio_rw = UIO_READ;
 -	UIO_SETUP_SYSSPACE(&uio);
 -
 -	return (process_domem(curlwp, l, &uio));
 +	return proc_readmem(curlwp, l, addr, value, sizeof(*value));
  }

  int
  ss_put_value(struct lwp *l, vaddr_t addr, u_int value)
  {
 -	struct uio uio;
 -	struct iovec iov;
 -
 -	iov.iov_base = (void *)&value;
 -	iov.iov_len = sizeof(u_int);
 -	uio.uio_iov = &iov;
 -	uio.uio_iovcnt = 1;
 -	uio.uio_offset = (off_t)addr;
 -	uio.uio_resid = sizeof(u_int);
 -	uio.uio_rw = UIO_WRITE;
 -	UIO_SETUP_SYSSPACE(&uio);
 -
 -	return (process_domem(curlwp, l, &uio));
 +	return proc_writemem(curlwp, l, addr, &value, sizeof(value));
  }

  void
 Index: sys/arch/hppa/include/ptrace.h
 ===================================================================
 RCS file: /cvsroot/src/sys/arch/hppa/include/ptrace.h,v
 retrieving revision 1.8
 diff -u -p -r1.8 ptrace.h
 --- sys/arch/hppa/include/ptrace.h	12 Apr 2017 18:17:59 -0000	1.8
 +++ sys/arch/hppa/include/ptrace.h	13 Apr 2017 10:20:42 -0000
 @@ -60,3 +60,7 @@
  #define PTRACE_BREAKPOINT	((const uint8_t[]) { 0x00, 0x01, 0x00, 0x04 })
  #define PTRACE_BREAKPOINT_ASM	__asm __volatile("break	%0, %1" :: "i" (HPPA_BREAK_KERNEL), "i" (HPPA_BREAK_SS) : "memory")
  #define PTRACE_BREAKPOINT_SIZE	4
 +
 +struct lwp;
 +int     process_clear_sstep(struct lwp *);
 +


 --------------080500010605080702030803--

From: "Nick Hudson" <skrll@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/52119 CVS commit: src/sys/arch/arm/arm32
Date: Mon, 17 Apr 2017 14:52:52 +0000

 Module Name:	src
 Committed By:	skrll
 Date:		Mon Apr 17 14:52:52 UTC 2017

 Modified Files:
 	src/sys/arch/arm/arm32: pmap.c

 Log Message:
 Perform icache syncs for ARM_MMU_EXTENDED as well.  This helps the PT_STEP
 code in pr/52119 and probably other things.


 To generate a diff of this commit:
 cvs rdiff -u -r1.344 -r1.345 src/sys/arch/arm/arm32/pmap.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

From: "Soren Jacobsen" <snj@netbsd.org>
To: gnats-bugs@gnats.NetBSD.org
Cc: 
Subject: PR/52119 CVS commit: [netbsd-7] src/sys/arch/arm/arm32
Date: Sat, 3 Jun 2017 17:01:31 +0000

 Module Name:	src
 Committed By:	snj
 Date:		Sat Jun  3 17:01:31 UTC 2017

 Modified Files:
 	src/sys/arch/arm/arm32 [netbsd-7]: pmap.c

 Log Message:
 Pull up following revision(s) (requested by skrll in ticket #1424):
 	sys/arch/arm/arm32/pmap.c: revision 1.345
 Perform icache syncs for ARM_MMU_EXTENDED as well.  This helps the PT_STEP
 code in pr/52119 and probably other things.


 To generate a diff of this commit:
 cvs rdiff -u -r1.295.2.10 -r1.295.2.11 src/sys/arch/arm/arm32/pmap.c

 Please note that diffs are not public domain; they are subject to the
 copyright notices on the relevant files.

State-Changed-From-To: open->feedback
State-Changed-By: bsiegert@NetBSD.org
State-Changed-When: Mon, 20 Aug 2018 18:16:14 +0000
State-Changed-Why:
Is this fixed?


State-Changed-From-To: feedback->open
State-Changed-By: kamil@NetBSD.org
State-Changed-When: Mon, 20 Aug 2018 20:20:11 +0200
State-Changed-Why:
Still valid in 8.99.24.
There is a plan to finish first threading features, before implementing PT_STEP for ARM.


>Unformatted:

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